//*****************************************************************************
//
//  am_mcu_apollo510_otpinfo1.h
//
//*****************************************************************************

//*****************************************************************************
//
// Copyright (c) 2025, Ambiq Micro, Inc.
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its
// contributors may be used to endorse or promote products derived from this
// software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision release_sdk5p0p0-5f68a8286b of the AmbiqSuite Development Package.
//
//*****************************************************************************

#ifndef AM_REG_OTP_INFO1_H
#define AM_REG_OTP_INFO1_H

#define AM_REG_OTP_INFO1_BASEADDR 0x42006000

#define AM_REG_OTP_INFO1_MRAM_RCVY_CNT0_O 0x00000800
#define AM_REG_OTP_INFO1_MRAM_RCVY_CNT0_ADDR 0x42006800
#define AM_REG_OTP_INFO1_MRAM_RCVY_CNT1_O 0x00000804
#define AM_REG_OTP_INFO1_MRAM_RCVY_CNT1_ADDR 0x42006804
#define AM_REG_OTP_INFO1_MAINPTR_O 0x00000810
#define AM_REG_OTP_INFO1_MAINPTR_ADDR 0x42006810
#define AM_REG_OTP_INFO1_SBLOTA_O 0x00000818
#define AM_REG_OTP_INFO1_SBLOTA_ADDR 0x42006818
#define AM_REG_OTP_INFO1_SOCID0_O 0x00000820
#define AM_REG_OTP_INFO1_SOCID0_ADDR 0x42006820
#define AM_REG_OTP_INFO1_SOCID1_O 0x00000824
#define AM_REG_OTP_INFO1_SOCID1_ADDR 0x42006824
#define AM_REG_OTP_INFO1_SOCID2_O 0x00000828
#define AM_REG_OTP_INFO1_SOCID2_ADDR 0x42006828
#define AM_REG_OTP_INFO1_SOCID3_O 0x0000082c
#define AM_REG_OTP_INFO1_SOCID3_ADDR 0x4200682c
#define AM_REG_OTP_INFO1_SOCID4_O 0x00000830
#define AM_REG_OTP_INFO1_SOCID4_ADDR 0x42006830
#define AM_REG_OTP_INFO1_SOCID5_O 0x00000834
#define AM_REG_OTP_INFO1_SOCID5_ADDR 0x42006834
#define AM_REG_OTP_INFO1_SOCID6_O 0x00000838
#define AM_REG_OTP_INFO1_SOCID6_ADDR 0x42006838
#define AM_REG_OTP_INFO1_SOCID7_O 0x0000083c
#define AM_REG_OTP_INFO1_SOCID7_ADDR 0x4200683c
#define AM_REG_OTP_INFO1_PATCH_TRACKER0_O 0x00000840
#define AM_REG_OTP_INFO1_PATCH_TRACKER0_ADDR 0x42006840
#define AM_REG_OTP_INFO1_PATCH_TRACKER1_O 0x00000844
#define AM_REG_OTP_INFO1_PATCH_TRACKER1_ADDR 0x42006844
#define AM_REG_OTP_INFO1_PATCH_TRACKER2_O 0x00000848
#define AM_REG_OTP_INFO1_PATCH_TRACKER2_ADDR 0x42006848
#define AM_REG_OTP_INFO1_PATCH_TRACKER3_O 0x0000084c
#define AM_REG_OTP_INFO1_PATCH_TRACKER3_ADDR 0x4200684c
#define AM_REG_OTP_INFO1_SBR_SDCERT_ADDR_O 0x00000850
#define AM_REG_OTP_INFO1_SBR_SDCERT_ADDR_ADDR 0x42006850
#define AM_REG_OTP_INFO1_SBR_IPT_ADDR_O 0x00000858
#define AM_REG_OTP_INFO1_SBR_IPT_ADDR_ADDR 0x42006858
#define AM_REG_OTP_INFO1_SBR_OPT_ADDR_O 0x0000085c
#define AM_REG_OTP_INFO1_SBR_OPT_ADDR_ADDR 0x4200685c
#define AM_REG_OTP_INFO1_TRIM_SBR_OTP_O 0x00000860
#define AM_REG_OTP_INFO1_TRIM_SBR_OTP_ADDR 0x42006860
#define AM_REG_OTP_INFO1_TEMP_CAL_ATE_O 0x00000900
#define AM_REG_OTP_INFO1_TEMP_CAL_ATE_ADDR 0x42006900
#define AM_REG_OTP_INFO1_TEMP_CAL_MEASURED_O 0x00000904
#define AM_REG_OTP_INFO1_TEMP_CAL_MEASURED_ADDR 0x42006904
#define AM_REG_OTP_INFO1_TEMP_CAL_ADC_OFFSET_O 0x00000908
#define AM_REG_OTP_INFO1_TEMP_CAL_ADC_OFFSET_ADDR 0x42006908
#define AM_REG_OTP_INFO1_CHIPSUBREV_O 0x0000090c
#define AM_REG_OTP_INFO1_CHIPSUBREV_ADDR 0x4200690c
#define AM_REG_OTP_INFO1_TRIM_REV_O 0x00000910
#define AM_REG_OTP_INFO1_TRIM_REV_ADDR 0x42006910
#define AM_REG_OTP_INFO1_FT1_GDR1_O 0x00000914
#define AM_REG_OTP_INFO1_FT1_GDR1_ADDR 0x42006914
#define AM_REG_OTP_INFO1_FT2_GDR1_O 0x00000918
#define AM_REG_OTP_INFO1_FT2_GDR1_ADDR 0x42006918
#define AM_REG_OTP_INFO1_LVT_TRIMCODE_O 0x0000091c
#define AM_REG_OTP_INFO1_LVT_TRIMCODE_ADDR 0x4200691c
#define AM_REG_OTP_INFO1_EHVT_TRIMCODE_O 0x00000920
#define AM_REG_OTP_INFO1_EHVT_TRIMCODE_ADDR 0x42006920
#define AM_REG_OTP_INFO1_ADC_GAIN_ERR_O 0x00000928
#define AM_REG_OTP_INFO1_ADC_GAIN_ERR_ADDR 0x42006928
#define AM_REG_OTP_INFO1_ADC_OFFSET_ERR_O 0x0000092c
#define AM_REG_OTP_INFO1_ADC_OFFSET_ERR_ADDR 0x4200692c
#define AM_REG_OTP_INFO1_AUDADC_A0_LG_OFFSET_O 0x00000940
#define AM_REG_OTP_INFO1_AUDADC_A0_LG_OFFSET_ADDR 0x42006940
#define AM_REG_OTP_INFO1_AUDADC_A0_HG_SLOPE_O 0x00000944
#define AM_REG_OTP_INFO1_AUDADC_A0_HG_SLOPE_ADDR 0x42006944
#define AM_REG_OTP_INFO1_AUDADC_A0_HG_INTERCEPT_O 0x00000948
#define AM_REG_OTP_INFO1_AUDADC_A0_HG_INTERCEPT_ADDR 0x42006948
#define AM_REG_OTP_INFO1_AUDADC_A1_LG_OFFSET_O 0x0000094c
#define AM_REG_OTP_INFO1_AUDADC_A1_LG_OFFSET_ADDR 0x4200694c
#define AM_REG_OTP_INFO1_AUDADC_A1_HG_SLOPE_O 0x00000950
#define AM_REG_OTP_INFO1_AUDADC_A1_HG_SLOPE_ADDR 0x42006950
#define AM_REG_OTP_INFO1_AUDADC_A1_HG_INTERCEPT_O 0x00000954
#define AM_REG_OTP_INFO1_AUDADC_A1_HG_INTERCEPT_ADDR 0x42006954
#define AM_REG_OTP_INFO1_AUDADC_B0_LG_OFFSET_O 0x00000958
#define AM_REG_OTP_INFO1_AUDADC_B0_LG_OFFSET_ADDR 0x42006958
#define AM_REG_OTP_INFO1_AUDADC_B0_HG_SLOPE_O 0x0000095c
#define AM_REG_OTP_INFO1_AUDADC_B0_HG_SLOPE_ADDR 0x4200695c
#define AM_REG_OTP_INFO1_AUDADC_B0_HG_INTERCEPT_O 0x00000960
#define AM_REG_OTP_INFO1_AUDADC_B0_HG_INTERCEPT_ADDR 0x42006960
#define AM_REG_OTP_INFO1_AUDADC_B1_LG_OFFSET_O 0x00000964
#define AM_REG_OTP_INFO1_AUDADC_B1_LG_OFFSET_ADDR 0x42006964
#define AM_REG_OTP_INFO1_AUDADC_B1_HG_SLOPE_O 0x00000968
#define AM_REG_OTP_INFO1_AUDADC_B1_HG_SLOPE_ADDR 0x42006968
#define AM_REG_OTP_INFO1_AUDADC_B1_HG_INTERCEPT_O 0x0000096c
#define AM_REG_OTP_INFO1_AUDADC_B1_HG_INTERCEPT_ADDR 0x4200696c
#define AM_REG_OTP_INFO1_POWERSTATE0_O 0x00000970
#define AM_REG_OTP_INFO1_POWERSTATE0_ADDR 0x42006970
#define AM_REG_OTP_INFO1_POWERSTATE1_O 0x00000974
#define AM_REG_OTP_INFO1_POWERSTATE1_ADDR 0x42006974
#define AM_REG_OTP_INFO1_POWERSTATE2_O 0x00000978
#define AM_REG_OTP_INFO1_POWERSTATE2_ADDR 0x42006978
#define AM_REG_OTP_INFO1_POWERSTATE3_O 0x0000097c
#define AM_REG_OTP_INFO1_POWERSTATE3_ADDR 0x4200697c
#define AM_REG_OTP_INFO1_POWERSTATE4_O 0x00000980
#define AM_REG_OTP_INFO1_POWERSTATE4_ADDR 0x42006980
#define AM_REG_OTP_INFO1_POWERSTATE5_O 0x00000984
#define AM_REG_OTP_INFO1_POWERSTATE5_ADDR 0x42006984
#define AM_REG_OTP_INFO1_POWERSTATE6_O 0x00000988
#define AM_REG_OTP_INFO1_POWERSTATE6_ADDR 0x42006988
#define AM_REG_OTP_INFO1_POWERSTATE7_O 0x0000098c
#define AM_REG_OTP_INFO1_POWERSTATE7_ADDR 0x4200698c
#define AM_REG_OTP_INFO1_POWERSTATE8_O 0x00000990
#define AM_REG_OTP_INFO1_POWERSTATE8_ADDR 0x42006990
#define AM_REG_OTP_INFO1_POWERSTATE9_O 0x00000994
#define AM_REG_OTP_INFO1_POWERSTATE9_ADDR 0x42006994
#define AM_REG_OTP_INFO1_POWERSTATE10_O 0x00000998
#define AM_REG_OTP_INFO1_POWERSTATE10_ADDR 0x42006998
#define AM_REG_OTP_INFO1_POWERSTATE11_O 0x0000099c
#define AM_REG_OTP_INFO1_POWERSTATE11_ADDR 0x4200699c
#define AM_REG_OTP_INFO1_POWERSTATE12_O 0x000009a0
#define AM_REG_OTP_INFO1_POWERSTATE12_ADDR 0x420069a0
#define AM_REG_OTP_INFO1_POWERSTATE13_O 0x000009a4
#define AM_REG_OTP_INFO1_POWERSTATE13_ADDR 0x420069a4
#define AM_REG_OTP_INFO1_POWERSTATE14_O 0x000009a8
#define AM_REG_OTP_INFO1_POWERSTATE14_ADDR 0x420069a8
#define AM_REG_OTP_INFO1_POWERSTATE15_O 0x000009ac
#define AM_REG_OTP_INFO1_POWERSTATE15_ADDR 0x420069ac
#define AM_REG_OTP_INFO1_POWERSTATE16_O 0x000009b0
#define AM_REG_OTP_INFO1_POWERSTATE16_ADDR 0x420069b0
#define AM_REG_OTP_INFO1_POWERSTATE17_O 0x000009b4
#define AM_REG_OTP_INFO1_POWERSTATE17_ADDR 0x420069b4
#define AM_REG_OTP_INFO1_POWERSTATE18_O 0x000009b8
#define AM_REG_OTP_INFO1_POWERSTATE18_ADDR 0x420069b8
#define AM_REG_OTP_INFO1_POWERSTATE19_O 0x000009bc
#define AM_REG_OTP_INFO1_POWERSTATE19_ADDR 0x420069bc
#define AM_REG_OTP_INFO1_GPUVDDCTON_O 0x000009c0
#define AM_REG_OTP_INFO1_GPUVDDCTON_ADDR 0x420069c0
#define AM_REG_OTP_INFO1_GPUVDDFTON_O 0x000009c4
#define AM_REG_OTP_INFO1_GPUVDDFTON_ADDR 0x420069c4
#define AM_REG_OTP_INFO1_STMTON_O 0x000009c8
#define AM_REG_OTP_INFO1_STMTON_ADDR 0x420069c8
#define AM_REG_OTP_INFO1_DEFAULTTON_O 0x000009cc
#define AM_REG_OTP_INFO1_DEFAULTTON_ADDR 0x420069cc
#define AM_REG_OTP_INFO1_VDDCLVACTTRIMADJ_O 0x000009d0
#define AM_REG_OTP_INFO1_VDDCLVACTTRIMADJ_ADDR 0x420069d0
#define AM_REG_OTP_INFO1_POWERSTATE_RSVD_D1_O 0x000009d4
#define AM_REG_OTP_INFO1_POWERSTATE_RSVD_D1_ADDR 0x420069d4
#define AM_REG_OTP_INFO1_POWERSTATE_RSVD_D2_O 0x000009d8
#define AM_REG_OTP_INFO1_POWERSTATE_RSVD_D2_ADDR 0x420069d8
#define AM_REG_OTP_INFO1_POWERSTATE_RSVD_D3_O 0x000009dc
#define AM_REG_OTP_INFO1_POWERSTATE_RSVD_D3_ADDR 0x420069dc
#define AM_REG_OTP_INFO1_MEMLDOCONFIG_O 0x000009e0
#define AM_REG_OTP_INFO1_MEMLDOCONFIG_ADDR 0x420069e0

// MRAM_RCVY_CNT0 - A bit count of the number of successful MRAM recoveries that have been done (0-31).  Each set bit equates to a successful MRAM recovery (of the AMBIQ recovery image). The count saturates at 31 = 0xFFFFFFFF (31 bits being set), additional counts (32-63) are logged in MRAM_RCVY_CNT1

// MRAM_RCVY_CNT1 - A bit count of the number of successful MRAM recoveries that have been done (32-64).  Each set bit equates to a successful MRAM recovery (of the AMBIQ recovery image). This field is not used until the MRAM_RCVY_CNT0 has been exhausted (31 = 0xFFFFFFFF), additional counts (32-63) are logged here

// MAINPTR - The location of the vector table of the main program. This value is read-only.
#define AM_REG_OTP_INFO1_MAINPTR_ADDRESS_S 0
#define AM_REG_OTP_INFO1_MAINPTR_ADDRESS_M 0xFFFFFFFF
#define AM_REG_OTP_INFO1_MAINPTR_ADDRESS(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
#define AM_REG_OTP_INFO1_MAINPTR_ADDRESS_Pos 0
#define AM_REG_OTP_INFO1_MAINPTR_ADDRESS_Msk 0xFFFFFFFF

// SBLOTA - This is the address of the slot to be used by the Secure Boot Loader for staging an upgrade.
#define AM_REG_OTP_INFO1_SBLOTA_ADDRESS_S 0
#define AM_REG_OTP_INFO1_SBLOTA_ADDRESS_M 0xFFFFFFFF
#define AM_REG_OTP_INFO1_SBLOTA_ADDRESS(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
#define AM_REG_OTP_INFO1_SBLOTA_ADDRESS_Pos 0
#define AM_REG_OTP_INFO1_SBLOTA_ADDRESS_Msk 0xFFFFFFFF

// SOCID0 - SoC_ID is a statistically unique identification for the device required for the creation of debug certificates.
#define AM_REG_OTP_INFO1_SOCID0_ID_S 0
#define AM_REG_OTP_INFO1_SOCID0_ID_M 0xFFFFFFFF
#define AM_REG_OTP_INFO1_SOCID0_ID(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
#define AM_REG_OTP_INFO1_SOCID0_ID_Pos 0
#define AM_REG_OTP_INFO1_SOCID0_ID_Msk 0xFFFFFFFF

// SOCID1 - SoC_ID is a statistically unique identification for the device required for the creation of debug certificates.
#define AM_REG_OTP_INFO1_SOCID1_ID_S 0
#define AM_REG_OTP_INFO1_SOCID1_ID_M 0xFFFFFFFF
#define AM_REG_OTP_INFO1_SOCID1_ID(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
#define AM_REG_OTP_INFO1_SOCID1_ID_Pos 0
#define AM_REG_OTP_INFO1_SOCID1_ID_Msk 0xFFFFFFFF

// SOCID2 - SoC_ID is a statistically unique identification for the device required for the creation of debug certificates.
#define AM_REG_OTP_INFO1_SOCID2_ID_S 0
#define AM_REG_OTP_INFO1_SOCID2_ID_M 0xFFFFFFFF
#define AM_REG_OTP_INFO1_SOCID2_ID(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
#define AM_REG_OTP_INFO1_SOCID2_ID_Pos 0
#define AM_REG_OTP_INFO1_SOCID2_ID_Msk 0xFFFFFFFF

// SOCID3 - SoC_ID is a statistically unique identification for the device required for the creation of debug certificates.
#define AM_REG_OTP_INFO1_SOCID3_ID_S 0
#define AM_REG_OTP_INFO1_SOCID3_ID_M 0xFFFFFFFF
#define AM_REG_OTP_INFO1_SOCID3_ID(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
#define AM_REG_OTP_INFO1_SOCID3_ID_Pos 0
#define AM_REG_OTP_INFO1_SOCID3_ID_Msk 0xFFFFFFFF

// SOCID4 - SoC_ID is a statistically unique identification for the device required for the creation of debug certificates.
#define AM_REG_OTP_INFO1_SOCID4_ID_S 0
#define AM_REG_OTP_INFO1_SOCID4_ID_M 0xFFFFFFFF
#define AM_REG_OTP_INFO1_SOCID4_ID(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
#define AM_REG_OTP_INFO1_SOCID4_ID_Pos 0
#define AM_REG_OTP_INFO1_SOCID4_ID_Msk 0xFFFFFFFF

// SOCID5 - SoC_ID is a statistically unique identification for the device required for the creation of debug certificates.
#define AM_REG_OTP_INFO1_SOCID5_ID_S 0
#define AM_REG_OTP_INFO1_SOCID5_ID_M 0xFFFFFFFF
#define AM_REG_OTP_INFO1_SOCID5_ID(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
#define AM_REG_OTP_INFO1_SOCID5_ID_Pos 0
#define AM_REG_OTP_INFO1_SOCID5_ID_Msk 0xFFFFFFFF

// SOCID6 - SoC_ID is a statistically unique identification for the device required for the creation of debug certificates.
#define AM_REG_OTP_INFO1_SOCID6_ID_S 0
#define AM_REG_OTP_INFO1_SOCID6_ID_M 0xFFFFFFFF
#define AM_REG_OTP_INFO1_SOCID6_ID(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
#define AM_REG_OTP_INFO1_SOCID6_ID_Pos 0
#define AM_REG_OTP_INFO1_SOCID6_ID_Msk 0xFFFFFFFF

// SOCID7 - SoC_ID is a statistically unique identification for the device required for the creation of debug certificates.
#define AM_REG_OTP_INFO1_SOCID7_ID_S 0
#define AM_REG_OTP_INFO1_SOCID7_ID_M 0xFFFFFFFF
#define AM_REG_OTP_INFO1_SOCID7_ID(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
#define AM_REG_OTP_INFO1_SOCID7_ID_Pos 0
#define AM_REG_OTP_INFO1_SOCID7_ID_Msk 0xFFFFFFFF

// PATCH_TRACKER0 - Apollo510 family SBL patch tracking [31:0]
#define AM_REG_OTP_INFO1_PATCH_TRACKER0_RSVD0_S 0
#define AM_REG_OTP_INFO1_PATCH_TRACKER0_RSVD0_M 0xFFFFFFFF
#define AM_REG_OTP_INFO1_PATCH_TRACKER0_RSVD0(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
#define AM_REG_OTP_INFO1_PATCH_TRACKER0_RSVD0_Pos 0
#define AM_REG_OTP_INFO1_PATCH_TRACKER0_RSVD0_Msk 0xFFFFFFFF

// PATCH_TRACKER1 - Apollo510 family SBL patch tracking [63:32]
#define AM_REG_OTP_INFO1_PATCH_TRACKER1_RSVD1_S 0
#define AM_REG_OTP_INFO1_PATCH_TRACKER1_RSVD1_M 0xFFFFFFFF
#define AM_REG_OTP_INFO1_PATCH_TRACKER1_RSVD1(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
#define AM_REG_OTP_INFO1_PATCH_TRACKER1_RSVD1_Pos 0
#define AM_REG_OTP_INFO1_PATCH_TRACKER1_RSVD1_Msk 0xFFFFFFFF

// PATCH_TRACKER2 - Apollo510 family SBL patch tracking [95:64]
#define AM_REG_OTP_INFO1_PATCH_TRACKER2_RSVD2_S 0
#define AM_REG_OTP_INFO1_PATCH_TRACKER2_RSVD2_M 0xFFFFFFFF
#define AM_REG_OTP_INFO1_PATCH_TRACKER2_RSVD2(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
#define AM_REG_OTP_INFO1_PATCH_TRACKER2_RSVD2_Pos 0
#define AM_REG_OTP_INFO1_PATCH_TRACKER2_RSVD2_Msk 0xFFFFFFFF

// PATCH_TRACKER3 - Apollo510 family SBL patch tracking [127:96]
#define AM_REG_OTP_INFO1_PATCH_TRACKER3_RSVD3_S 0
#define AM_REG_OTP_INFO1_PATCH_TRACKER3_RSVD3_M 0xFFFFFFFF
#define AM_REG_OTP_INFO1_PATCH_TRACKER3_RSVD3(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
#define AM_REG_OTP_INFO1_PATCH_TRACKER3_RSVD3_Pos 0
#define AM_REG_OTP_INFO1_PATCH_TRACKER3_RSVD3_Msk 0xFFFFFFFF

// SBR_SDCERT_ADDR - A pointer to the SD certificate.
#define AM_REG_OTP_INFO1_SBR_SDCERT_ADDR_ICV_S 0
#define AM_REG_OTP_INFO1_SBR_SDCERT_ADDR_ICV_M 0xFFFFFFFF
#define AM_REG_OTP_INFO1_SBR_SDCERT_ADDR_ICV(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
#define AM_REG_OTP_INFO1_SBR_SDCERT_ADDR_ICV_Pos 0
#define AM_REG_OTP_INFO1_SBR_SDCERT_ADDR_ICV_Msk 0xFFFFFFFF

// SBR_IPT_ADDR - A pointer to the SBR IPT.
#define AM_REG_OTP_INFO1_SBR_IPT_ADDR_ADDRESS_S 0
#define AM_REG_OTP_INFO1_SBR_IPT_ADDR_ADDRESS_M 0xFFFFFFFF
#define AM_REG_OTP_INFO1_SBR_IPT_ADDR_ADDRESS(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
#define AM_REG_OTP_INFO1_SBR_IPT_ADDR_ADDRESS_Pos 0
#define AM_REG_OTP_INFO1_SBR_IPT_ADDR_ADDRESS_Msk 0xFFFFFFFF

// SBR_OPT_ADDR - A pointer to the SBR OPT.
#define AM_REG_OTP_INFO1_SBR_OPT_ADDR_ADDRESS_S 0
#define AM_REG_OTP_INFO1_SBR_OPT_ADDR_ADDRESS_M 0xFFFFFFFF
#define AM_REG_OTP_INFO1_SBR_OPT_ADDR_ADDRESS(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
#define AM_REG_OTP_INFO1_SBR_OPT_ADDR_ADDRESS_Pos 0
#define AM_REG_OTP_INFO1_SBR_OPT_ADDR_ADDRESS_Msk 0xFFFFFFFF

// TRIM_SBR_OTP - This register configures the SBR for how it will handle OTP errors during the boot process.
#define AM_REG_OTP_INFO1_TRIM_SBR_OTP_RESVD20_S 20
#define AM_REG_OTP_INFO1_TRIM_SBR_OTP_RESVD20_M 0xFFF00000
#define AM_REG_OTP_INFO1_TRIM_SBR_OTP_RESVD20(n) (((uint32_t)(n) << 20) & 0xFFF00000)
#define AM_REG_OTP_INFO1_TRIM_SBR_OTP_RESVD20_Pos 20
#define AM_REG_OTP_INFO1_TRIM_SBR_OTP_RESVD20_Msk 0xFFF00000
#define AM_REG_OTP_INFO1_TRIM_SBR_OTP_MAX_OTP_RETRY_S 12
#define AM_REG_OTP_INFO1_TRIM_SBR_OTP_MAX_OTP_RETRY_M 0x000FF000
#define AM_REG_OTP_INFO1_TRIM_SBR_OTP_MAX_OTP_RETRY(n) (((uint32_t)(n) << 12) & 0x000FF000)
#define AM_REG_OTP_INFO1_TRIM_SBR_OTP_MAX_OTP_RETRY_Pos 12
#define AM_REG_OTP_INFO1_TRIM_SBR_OTP_MAX_OTP_RETRY_Msk 0x000FF000
#define AM_REG_OTP_INFO1_TRIM_SBR_OTP_RESVD10_S 10
#define AM_REG_OTP_INFO1_TRIM_SBR_OTP_RESVD10_M 0x00000C00
#define AM_REG_OTP_INFO1_TRIM_SBR_OTP_RESVD10(n) (((uint32_t)(n) << 10) & 0x00000C00)
#define AM_REG_OTP_INFO1_TRIM_SBR_OTP_RESVD10_Pos 10
#define AM_REG_OTP_INFO1_TRIM_SBR_OTP_RESVD10_Msk 0x00000C00
#define AM_REG_OTP_INFO1_TRIM_SBR_OTP_INT_MASK_S 0
#define AM_REG_OTP_INFO1_TRIM_SBR_OTP_INT_MASK_M 0x000003FF
#define AM_REG_OTP_INFO1_TRIM_SBR_OTP_INT_MASK(n) (((uint32_t)(n) << 0) & 0x000003FF)
#define AM_REG_OTP_INFO1_TRIM_SBR_OTP_INT_MASK_Pos 0
#define AM_REG_OTP_INFO1_TRIM_SBR_OTP_INT_MASK_Msk 0x000003FF

// TEMP_CAL_ATE - The temperature measured on the ATE test head when the part's temperature sensor was calibrated.
#define AM_REG_OTP_INFO1_TEMP_CAL_ATE_TEMPERATURE_S 0
#define AM_REG_OTP_INFO1_TEMP_CAL_ATE_TEMPERATURE_M 0xFFFFFFFF
#define AM_REG_OTP_INFO1_TEMP_CAL_ATE_TEMPERATURE(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
#define AM_REG_OTP_INFO1_TEMP_CAL_ATE_TEMPERATURE_Pos 0
#define AM_REG_OTP_INFO1_TEMP_CAL_ATE_TEMPERATURE_Msk 0xFFFFFFFF

// TEMP_CAL_MEASURED - The voltage measured on the analog test mux output when the part's temperature sensor was calibrated.
#define AM_REG_OTP_INFO1_TEMP_CAL_MEASURED_VOLTS_S 0
#define AM_REG_OTP_INFO1_TEMP_CAL_MEASURED_VOLTS_M 0xFFFFFFFF
#define AM_REG_OTP_INFO1_TEMP_CAL_MEASURED_VOLTS(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
#define AM_REG_OTP_INFO1_TEMP_CAL_MEASURED_VOLTS_Pos 0
#define AM_REG_OTP_INFO1_TEMP_CAL_MEASURED_VOLTS_Msk 0xFFFFFFFF

// TEMP_CAL_ADC_OFFSET - The offset voltage measured on for the ADC when the part's temperature sensor was calibrated.
#define AM_REG_OTP_INFO1_TEMP_CAL_ADC_OFFSET_VOLTS_S 0
#define AM_REG_OTP_INFO1_TEMP_CAL_ADC_OFFSET_VOLTS_M 0xFFFFFFFF
#define AM_REG_OTP_INFO1_TEMP_CAL_ADC_OFFSET_VOLTS(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
#define AM_REG_OTP_INFO1_TEMP_CAL_ADC_OFFSET_VOLTS_Pos 0
#define AM_REG_OTP_INFO1_TEMP_CAL_ADC_OFFSET_VOLTS_Msk 0xFFFFFFFF

// CHIPSUBREV -
#define AM_REG_OTP_INFO1_CHIPSUBREV_SUBREV_S 0
#define AM_REG_OTP_INFO1_CHIPSUBREV_SUBREV_M 0xFFFFFFFF
#define AM_REG_OTP_INFO1_CHIPSUBREV_SUBREV(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
#define AM_REG_OTP_INFO1_CHIPSUBREV_SUBREV_Pos 0
#define AM_REG_OTP_INFO1_CHIPSUBREV_SUBREV_Msk 0xFFFFFFFF

// TRIM_REV - Contains the trim revision number.
#define AM_REG_OTP_INFO1_TRIM_REV_REVNUM_S 0
#define AM_REG_OTP_INFO1_TRIM_REV_REVNUM_M 0xFFFFFFFF
#define AM_REG_OTP_INFO1_TRIM_REV_REVNUM(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
#define AM_REG_OTP_INFO1_TRIM_REV_REVNUM_Pos 0
#define AM_REG_OTP_INFO1_TRIM_REV_REVNUM_Msk 0xFFFFFFFF

// FT1_GDR1 - Copy of FT1 GDR1
#define AM_REG_OTP_INFO1_FT1_GDR1_FTVAL_S 0
#define AM_REG_OTP_INFO1_FT1_GDR1_FTVAL_M 0xFFFFFFFF
#define AM_REG_OTP_INFO1_FT1_GDR1_FTVAL(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
#define AM_REG_OTP_INFO1_FT1_GDR1_FTVAL_Pos 0
#define AM_REG_OTP_INFO1_FT1_GDR1_FTVAL_Msk 0xFFFFFFFF

// FT2_GDR1 - Copy of FT2 GDR1
#define AM_REG_OTP_INFO1_FT2_GDR1_FTVAL_S 0
#define AM_REG_OTP_INFO1_FT2_GDR1_FTVAL_M 0xFFFFFFFF
#define AM_REG_OTP_INFO1_FT2_GDR1_FTVAL(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
#define AM_REG_OTP_INFO1_FT2_GDR1_FTVAL_Pos 0
#define AM_REG_OTP_INFO1_FT2_GDR1_FTVAL_Msk 0xFFFFFFFF

// LVT_TRIMCODE - LVT trim code value.
#define AM_REG_OTP_INFO1_LVT_TRIMCODE_TRIMCODE_S 0
#define AM_REG_OTP_INFO1_LVT_TRIMCODE_TRIMCODE_M 0xFFFFFFFF
#define AM_REG_OTP_INFO1_LVT_TRIMCODE_TRIMCODE(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
#define AM_REG_OTP_INFO1_LVT_TRIMCODE_TRIMCODE_Pos 0
#define AM_REG_OTP_INFO1_LVT_TRIMCODE_TRIMCODE_Msk 0xFFFFFFFF

// EHVT_TRIMCODE - EHVT trim code value.
#define AM_REG_OTP_INFO1_EHVT_TRIMCODE_TRIMCODE_S 0
#define AM_REG_OTP_INFO1_EHVT_TRIMCODE_TRIMCODE_M 0xFFFFFFFF
#define AM_REG_OTP_INFO1_EHVT_TRIMCODE_TRIMCODE(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
#define AM_REG_OTP_INFO1_EHVT_TRIMCODE_TRIMCODE_Pos 0
#define AM_REG_OTP_INFO1_EHVT_TRIMCODE_TRIMCODE_Msk 0xFFFFFFFF

// ADC_GAIN_ERR - This float value is the ADC gain error used for correcting the error from ADC measurement.
#define AM_REG_OTP_INFO1_ADC_GAIN_ERR_ERROR_S 0
#define AM_REG_OTP_INFO1_ADC_GAIN_ERR_ERROR_M 0xFFFFFFFF
#define AM_REG_OTP_INFO1_ADC_GAIN_ERR_ERROR(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
#define AM_REG_OTP_INFO1_ADC_GAIN_ERR_ERROR_Pos 0
#define AM_REG_OTP_INFO1_ADC_GAIN_ERR_ERROR_Msk 0xFFFFFFFF

// ADC_OFFSET_ERR - This float value is the ADC offset (volts).
#define AM_REG_OTP_INFO1_ADC_OFFSET_ERR_OFFSET_S 0
#define AM_REG_OTP_INFO1_ADC_OFFSET_ERR_OFFSET_M 0xFFFFFFFF
#define AM_REG_OTP_INFO1_ADC_OFFSET_ERR_OFFSET(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
#define AM_REG_OTP_INFO1_ADC_OFFSET_ERR_OFFSET_Pos 0
#define AM_REG_OTP_INFO1_ADC_OFFSET_ERR_OFFSET_Msk 0xFFFFFFFF

// AUDADC_A0_LG_OFFSET - This is the float value for low gain offset (less than 12dB). A0 maps to Slot 0
#define AM_REG_OTP_INFO1_AUDADC_A0_LG_OFFSET_LGOFFSET_S 0
#define AM_REG_OTP_INFO1_AUDADC_A0_LG_OFFSET_LGOFFSET_M 0xFFFFFFFF
#define AM_REG_OTP_INFO1_AUDADC_A0_LG_OFFSET_LGOFFSET(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
#define AM_REG_OTP_INFO1_AUDADC_A0_LG_OFFSET_LGOFFSET_Pos 0
#define AM_REG_OTP_INFO1_AUDADC_A0_LG_OFFSET_LGOFFSET_Msk 0xFFFFFFFF

// AUDADC_A0_HG_SLOPE - This is the float value for high gain slope (more than 12dB). A0 maps to Slot 0
#define AM_REG_OTP_INFO1_AUDADC_A0_HG_SLOPE_HGSLOPE_S 0
#define AM_REG_OTP_INFO1_AUDADC_A0_HG_SLOPE_HGSLOPE_M 0xFFFFFFFF
#define AM_REG_OTP_INFO1_AUDADC_A0_HG_SLOPE_HGSLOPE(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
#define AM_REG_OTP_INFO1_AUDADC_A0_HG_SLOPE_HGSLOPE_Pos 0
#define AM_REG_OTP_INFO1_AUDADC_A0_HG_SLOPE_HGSLOPE_Msk 0xFFFFFFFF

// AUDADC_A0_HG_INTERCEPT - This is the float value for high gain intercept (more than 12dB). A0 maps to Slot 0
#define AM_REG_OTP_INFO1_AUDADC_A0_HG_INTERCEPT_HGINTERCEPT_S 0
#define AM_REG_OTP_INFO1_AUDADC_A0_HG_INTERCEPT_HGINTERCEPT_M 0xFFFFFFFF
#define AM_REG_OTP_INFO1_AUDADC_A0_HG_INTERCEPT_HGINTERCEPT(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
#define AM_REG_OTP_INFO1_AUDADC_A0_HG_INTERCEPT_HGINTERCEPT_Pos 0
#define AM_REG_OTP_INFO1_AUDADC_A0_HG_INTERCEPT_HGINTERCEPT_Msk 0xFFFFFFFF

// AUDADC_A1_LG_OFFSET - This is the float value for low gain offset (less than 12dB). A1 maps to Slot 1
#define AM_REG_OTP_INFO1_AUDADC_A1_LG_OFFSET_LGOFFSET_S 0
#define AM_REG_OTP_INFO1_AUDADC_A1_LG_OFFSET_LGOFFSET_M 0xFFFFFFFF
#define AM_REG_OTP_INFO1_AUDADC_A1_LG_OFFSET_LGOFFSET(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
#define AM_REG_OTP_INFO1_AUDADC_A1_LG_OFFSET_LGOFFSET_Pos 0
#define AM_REG_OTP_INFO1_AUDADC_A1_LG_OFFSET_LGOFFSET_Msk 0xFFFFFFFF

// AUDADC_A1_HG_SLOPE - This is the float value for high gain slope (more than 12dB). A1 maps to Slot 1
#define AM_REG_OTP_INFO1_AUDADC_A1_HG_SLOPE_HGSLOPE_S 0
#define AM_REG_OTP_INFO1_AUDADC_A1_HG_SLOPE_HGSLOPE_M 0xFFFFFFFF
#define AM_REG_OTP_INFO1_AUDADC_A1_HG_SLOPE_HGSLOPE(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
#define AM_REG_OTP_INFO1_AUDADC_A1_HG_SLOPE_HGSLOPE_Pos 0
#define AM_REG_OTP_INFO1_AUDADC_A1_HG_SLOPE_HGSLOPE_Msk 0xFFFFFFFF

// AUDADC_A1_HG_INTERCEPT - This is the float value for high gain intercept (more than 12dB). A1 maps to Slot 1
#define AM_REG_OTP_INFO1_AUDADC_A1_HG_INTERCEPT_HGINTERCEPT_S 0
#define AM_REG_OTP_INFO1_AUDADC_A1_HG_INTERCEPT_HGINTERCEPT_M 0xFFFFFFFF
#define AM_REG_OTP_INFO1_AUDADC_A1_HG_INTERCEPT_HGINTERCEPT(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
#define AM_REG_OTP_INFO1_AUDADC_A1_HG_INTERCEPT_HGINTERCEPT_Pos 0
#define AM_REG_OTP_INFO1_AUDADC_A1_HG_INTERCEPT_HGINTERCEPT_Msk 0xFFFFFFFF

// AUDADC_B0_LG_OFFSET - This is the float value for low gain offset (less than 12dB). B0 maps to Slot 2
#define AM_REG_OTP_INFO1_AUDADC_B0_LG_OFFSET_LGOFFSET_S 0
#define AM_REG_OTP_INFO1_AUDADC_B0_LG_OFFSET_LGOFFSET_M 0xFFFFFFFF
#define AM_REG_OTP_INFO1_AUDADC_B0_LG_OFFSET_LGOFFSET(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
#define AM_REG_OTP_INFO1_AUDADC_B0_LG_OFFSET_LGOFFSET_Pos 0
#define AM_REG_OTP_INFO1_AUDADC_B0_LG_OFFSET_LGOFFSET_Msk 0xFFFFFFFF

// AUDADC_B0_HG_SLOPE - This is the float value for high gain slope (more than 12dB). B0 maps to Slot 2
#define AM_REG_OTP_INFO1_AUDADC_B0_HG_SLOPE_HGSLOPE_S 0
#define AM_REG_OTP_INFO1_AUDADC_B0_HG_SLOPE_HGSLOPE_M 0xFFFFFFFF
#define AM_REG_OTP_INFO1_AUDADC_B0_HG_SLOPE_HGSLOPE(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
#define AM_REG_OTP_INFO1_AUDADC_B0_HG_SLOPE_HGSLOPE_Pos 0
#define AM_REG_OTP_INFO1_AUDADC_B0_HG_SLOPE_HGSLOPE_Msk 0xFFFFFFFF

// AUDADC_B0_HG_INTERCEPT - This is the float value for high gain intercept (more than 12dB). B0 maps to Slot 2
#define AM_REG_OTP_INFO1_AUDADC_B0_HG_INTERCEPT_HGINTERCEPT_S 0
#define AM_REG_OTP_INFO1_AUDADC_B0_HG_INTERCEPT_HGINTERCEPT_M 0xFFFFFFFF
#define AM_REG_OTP_INFO1_AUDADC_B0_HG_INTERCEPT_HGINTERCEPT(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
#define AM_REG_OTP_INFO1_AUDADC_B0_HG_INTERCEPT_HGINTERCEPT_Pos 0
#define AM_REG_OTP_INFO1_AUDADC_B0_HG_INTERCEPT_HGINTERCEPT_Msk 0xFFFFFFFF

// AUDADC_B1_LG_OFFSET - This is the float value for low gain offset (less than 12dB). B1 maps to Slot 3
#define AM_REG_OTP_INFO1_AUDADC_B1_LG_OFFSET_LGOFFSET_S 0
#define AM_REG_OTP_INFO1_AUDADC_B1_LG_OFFSET_LGOFFSET_M 0xFFFFFFFF
#define AM_REG_OTP_INFO1_AUDADC_B1_LG_OFFSET_LGOFFSET(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
#define AM_REG_OTP_INFO1_AUDADC_B1_LG_OFFSET_LGOFFSET_Pos 0
#define AM_REG_OTP_INFO1_AUDADC_B1_LG_OFFSET_LGOFFSET_Msk 0xFFFFFFFF

// AUDADC_B1_HG_SLOPE - This is the float value for high gain slope (more than 12dB). B1 maps to Slot 3
#define AM_REG_OTP_INFO1_AUDADC_B1_HG_SLOPE_HGSLOPE_S 0
#define AM_REG_OTP_INFO1_AUDADC_B1_HG_SLOPE_HGSLOPE_M 0xFFFFFFFF
#define AM_REG_OTP_INFO1_AUDADC_B1_HG_SLOPE_HGSLOPE(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
#define AM_REG_OTP_INFO1_AUDADC_B1_HG_SLOPE_HGSLOPE_Pos 0
#define AM_REG_OTP_INFO1_AUDADC_B1_HG_SLOPE_HGSLOPE_Msk 0xFFFFFFFF

// AUDADC_B1_HG_INTERCEPT - This is the float value for high gain intercept (more than 12dB). B1 maps to Slot 3
#define AM_REG_OTP_INFO1_AUDADC_B1_HG_INTERCEPT_HGINTERCEPT_S 0
#define AM_REG_OTP_INFO1_AUDADC_B1_HG_INTERCEPT_HGINTERCEPT_M 0xFFFFFFFF
#define AM_REG_OTP_INFO1_AUDADC_B1_HG_INTERCEPT_HGINTERCEPT(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
#define AM_REG_OTP_INFO1_AUDADC_B1_HG_INTERCEPT_HGINTERCEPT_Pos 0
#define AM_REG_OTP_INFO1_AUDADC_B1_HG_INTERCEPT_HGINTERCEPT_Msk 0xFFFFFFFF

// POWERSTATE0 - Power state register. CPU LP mode, GPU off, XYZ peripherals off. Temperature range greater than 50C.
#define AM_REG_OTP_INFO1_POWERSTATE0_RESVD29_S 29
#define AM_REG_OTP_INFO1_POWERSTATE0_RESVD29_M 0xE0000000
#define AM_REG_OTP_INFO1_POWERSTATE0_RESVD29(n) (((uint32_t)(n) << 29) & 0xE0000000)
#define AM_REG_OTP_INFO1_POWERSTATE0_RESVD29_Pos 29
#define AM_REG_OTP_INFO1_POWERSTATE0_RESVD29_Msk 0xE0000000
#define AM_REG_OTP_INFO1_POWERSTATE0_TVRGCVREFSEL_S 28
#define AM_REG_OTP_INFO1_POWERSTATE0_TVRGCVREFSEL_M 0x10000000
#define AM_REG_OTP_INFO1_POWERSTATE0_TVRGCVREFSEL(n) (((uint32_t)(n) << 28) & 0x10000000)
#define AM_REG_OTP_INFO1_POWERSTATE0_TVRGCVREFSEL_Pos 28
#define AM_REG_OTP_INFO1_POWERSTATE0_TVRGCVREFSEL_Msk 0x10000000
#define AM_REG_OTP_INFO1_POWERSTATE0_TVRGCACTTRIM_S 21
#define AM_REG_OTP_INFO1_POWERSTATE0_TVRGCACTTRIM_M 0x0FE00000
#define AM_REG_OTP_INFO1_POWERSTATE0_TVRGCACTTRIM(n) (((uint32_t)(n) << 21) & 0x0FE00000)
#define AM_REG_OTP_INFO1_POWERSTATE0_TVRGCACTTRIM_Pos 21
#define AM_REG_OTP_INFO1_POWERSTATE0_TVRGCACTTRIM_Msk 0x0FE00000
#define AM_REG_OTP_INFO1_POWERSTATE0_CORELDOTEMPCOTRIM_S 17
#define AM_REG_OTP_INFO1_POWERSTATE0_CORELDOTEMPCOTRIM_M 0x001E0000
#define AM_REG_OTP_INFO1_POWERSTATE0_CORELDOTEMPCOTRIM(n) (((uint32_t)(n) << 17) & 0x001E0000)
#define AM_REG_OTP_INFO1_POWERSTATE0_CORELDOTEMPCOTRIM_Pos 17
#define AM_REG_OTP_INFO1_POWERSTATE0_CORELDOTEMPCOTRIM_Msk 0x001E0000
#define AM_REG_OTP_INFO1_POWERSTATE0_CORELDOACTTRIM_S 7
#define AM_REG_OTP_INFO1_POWERSTATE0_CORELDOACTTRIM_M 0x0001FF80
#define AM_REG_OTP_INFO1_POWERSTATE0_CORELDOACTTRIM(n) (((uint32_t)(n) << 7) & 0x0001FF80)
#define AM_REG_OTP_INFO1_POWERSTATE0_CORELDOACTTRIM_Pos 7
#define AM_REG_OTP_INFO1_POWERSTATE0_CORELDOACTTRIM_Msk 0x0001FF80
#define AM_REG_OTP_INFO1_POWERSTATE0_TVRGFACTTRIM_S 0
#define AM_REG_OTP_INFO1_POWERSTATE0_TVRGFACTTRIM_M 0x0000007F
#define AM_REG_OTP_INFO1_POWERSTATE0_TVRGFACTTRIM(n) (((uint32_t)(n) << 0) & 0x0000007F)
#define AM_REG_OTP_INFO1_POWERSTATE0_TVRGFACTTRIM_Pos 0
#define AM_REG_OTP_INFO1_POWERSTATE0_TVRGFACTTRIM_Msk 0x0000007F

// POWERSTATE1 - Power state register. CPU LP mode, GPU off, XYZ peripherals off. Temperature range 0C to 50C.
#define AM_REG_OTP_INFO1_POWERSTATE1_RESVD29_S 29
#define AM_REG_OTP_INFO1_POWERSTATE1_RESVD29_M 0xE0000000
#define AM_REG_OTP_INFO1_POWERSTATE1_RESVD29(n) (((uint32_t)(n) << 29) & 0xE0000000)
#define AM_REG_OTP_INFO1_POWERSTATE1_RESVD29_Pos 29
#define AM_REG_OTP_INFO1_POWERSTATE1_RESVD29_Msk 0xE0000000
#define AM_REG_OTP_INFO1_POWERSTATE1_TVRGCVREFSEL_S 28
#define AM_REG_OTP_INFO1_POWERSTATE1_TVRGCVREFSEL_M 0x10000000
#define AM_REG_OTP_INFO1_POWERSTATE1_TVRGCVREFSEL(n) (((uint32_t)(n) << 28) & 0x10000000)
#define AM_REG_OTP_INFO1_POWERSTATE1_TVRGCVREFSEL_Pos 28
#define AM_REG_OTP_INFO1_POWERSTATE1_TVRGCVREFSEL_Msk 0x10000000
#define AM_REG_OTP_INFO1_POWERSTATE1_TVRGCACTTRIM_S 21
#define AM_REG_OTP_INFO1_POWERSTATE1_TVRGCACTTRIM_M 0x0FE00000
#define AM_REG_OTP_INFO1_POWERSTATE1_TVRGCACTTRIM(n) (((uint32_t)(n) << 21) & 0x0FE00000)
#define AM_REG_OTP_INFO1_POWERSTATE1_TVRGCACTTRIM_Pos 21
#define AM_REG_OTP_INFO1_POWERSTATE1_TVRGCACTTRIM_Msk 0x0FE00000
#define AM_REG_OTP_INFO1_POWERSTATE1_CORELDOTEMPCOTRIM_S 17
#define AM_REG_OTP_INFO1_POWERSTATE1_CORELDOTEMPCOTRIM_M 0x001E0000
#define AM_REG_OTP_INFO1_POWERSTATE1_CORELDOTEMPCOTRIM(n) (((uint32_t)(n) << 17) & 0x001E0000)
#define AM_REG_OTP_INFO1_POWERSTATE1_CORELDOTEMPCOTRIM_Pos 17
#define AM_REG_OTP_INFO1_POWERSTATE1_CORELDOTEMPCOTRIM_Msk 0x001E0000
#define AM_REG_OTP_INFO1_POWERSTATE1_CORELDOACTTRIM_S 7
#define AM_REG_OTP_INFO1_POWERSTATE1_CORELDOACTTRIM_M 0x0001FF80
#define AM_REG_OTP_INFO1_POWERSTATE1_CORELDOACTTRIM(n) (((uint32_t)(n) << 7) & 0x0001FF80)
#define AM_REG_OTP_INFO1_POWERSTATE1_CORELDOACTTRIM_Pos 7
#define AM_REG_OTP_INFO1_POWERSTATE1_CORELDOACTTRIM_Msk 0x0001FF80
#define AM_REG_OTP_INFO1_POWERSTATE1_TVRGFACTTRIM_S 0
#define AM_REG_OTP_INFO1_POWERSTATE1_TVRGFACTTRIM_M 0x0000007F
#define AM_REG_OTP_INFO1_POWERSTATE1_TVRGFACTTRIM(n) (((uint32_t)(n) << 0) & 0x0000007F)
#define AM_REG_OTP_INFO1_POWERSTATE1_TVRGFACTTRIM_Pos 0
#define AM_REG_OTP_INFO1_POWERSTATE1_TVRGFACTTRIM_Msk 0x0000007F

// POWERSTATE2 - Power state register. CPU LP mode, GPU off, XYZ peripherals off. Temperature range -20C to 0C.
#define AM_REG_OTP_INFO1_POWERSTATE2_RESVD29_S 29
#define AM_REG_OTP_INFO1_POWERSTATE2_RESVD29_M 0xE0000000
#define AM_REG_OTP_INFO1_POWERSTATE2_RESVD29(n) (((uint32_t)(n) << 29) & 0xE0000000)
#define AM_REG_OTP_INFO1_POWERSTATE2_RESVD29_Pos 29
#define AM_REG_OTP_INFO1_POWERSTATE2_RESVD29_Msk 0xE0000000
#define AM_REG_OTP_INFO1_POWERSTATE2_TVRGCVREFSEL_S 28
#define AM_REG_OTP_INFO1_POWERSTATE2_TVRGCVREFSEL_M 0x10000000
#define AM_REG_OTP_INFO1_POWERSTATE2_TVRGCVREFSEL(n) (((uint32_t)(n) << 28) & 0x10000000)
#define AM_REG_OTP_INFO1_POWERSTATE2_TVRGCVREFSEL_Pos 28
#define AM_REG_OTP_INFO1_POWERSTATE2_TVRGCVREFSEL_Msk 0x10000000
#define AM_REG_OTP_INFO1_POWERSTATE2_TVRGCACTTRIM_S 21
#define AM_REG_OTP_INFO1_POWERSTATE2_TVRGCACTTRIM_M 0x0FE00000
#define AM_REG_OTP_INFO1_POWERSTATE2_TVRGCACTTRIM(n) (((uint32_t)(n) << 21) & 0x0FE00000)
#define AM_REG_OTP_INFO1_POWERSTATE2_TVRGCACTTRIM_Pos 21
#define AM_REG_OTP_INFO1_POWERSTATE2_TVRGCACTTRIM_Msk 0x0FE00000
#define AM_REG_OTP_INFO1_POWERSTATE2_CORELDOTEMPCOTRIM_S 17
#define AM_REG_OTP_INFO1_POWERSTATE2_CORELDOTEMPCOTRIM_M 0x001E0000
#define AM_REG_OTP_INFO1_POWERSTATE2_CORELDOTEMPCOTRIM(n) (((uint32_t)(n) << 17) & 0x001E0000)
#define AM_REG_OTP_INFO1_POWERSTATE2_CORELDOTEMPCOTRIM_Pos 17
#define AM_REG_OTP_INFO1_POWERSTATE2_CORELDOTEMPCOTRIM_Msk 0x001E0000
#define AM_REG_OTP_INFO1_POWERSTATE2_CORELDOACTTRIM_S 7
#define AM_REG_OTP_INFO1_POWERSTATE2_CORELDOACTTRIM_M 0x0001FF80
#define AM_REG_OTP_INFO1_POWERSTATE2_CORELDOACTTRIM(n) (((uint32_t)(n) << 7) & 0x0001FF80)
#define AM_REG_OTP_INFO1_POWERSTATE2_CORELDOACTTRIM_Pos 7
#define AM_REG_OTP_INFO1_POWERSTATE2_CORELDOACTTRIM_Msk 0x0001FF80
#define AM_REG_OTP_INFO1_POWERSTATE2_TVRGFACTTRIM_S 0
#define AM_REG_OTP_INFO1_POWERSTATE2_TVRGFACTTRIM_M 0x0000007F
#define AM_REG_OTP_INFO1_POWERSTATE2_TVRGFACTTRIM(n) (((uint32_t)(n) << 0) & 0x0000007F)
#define AM_REG_OTP_INFO1_POWERSTATE2_TVRGFACTTRIM_Pos 0
#define AM_REG_OTP_INFO1_POWERSTATE2_TVRGFACTTRIM_Msk 0x0000007F

// POWERSTATE3 - Power state register. CPU LP mode, GPU off, XYZ peripherals off. Temperature range -40C to -20C.
#define AM_REG_OTP_INFO1_POWERSTATE3_RESVD29_S 29
#define AM_REG_OTP_INFO1_POWERSTATE3_RESVD29_M 0xE0000000
#define AM_REG_OTP_INFO1_POWERSTATE3_RESVD29(n) (((uint32_t)(n) << 29) & 0xE0000000)
#define AM_REG_OTP_INFO1_POWERSTATE3_RESVD29_Pos 29
#define AM_REG_OTP_INFO1_POWERSTATE3_RESVD29_Msk 0xE0000000
#define AM_REG_OTP_INFO1_POWERSTATE3_TVRGCVREFSEL_S 28
#define AM_REG_OTP_INFO1_POWERSTATE3_TVRGCVREFSEL_M 0x10000000
#define AM_REG_OTP_INFO1_POWERSTATE3_TVRGCVREFSEL(n) (((uint32_t)(n) << 28) & 0x10000000)
#define AM_REG_OTP_INFO1_POWERSTATE3_TVRGCVREFSEL_Pos 28
#define AM_REG_OTP_INFO1_POWERSTATE3_TVRGCVREFSEL_Msk 0x10000000
#define AM_REG_OTP_INFO1_POWERSTATE3_TVRGCACTTRIM_S 21
#define AM_REG_OTP_INFO1_POWERSTATE3_TVRGCACTTRIM_M 0x0FE00000
#define AM_REG_OTP_INFO1_POWERSTATE3_TVRGCACTTRIM(n) (((uint32_t)(n) << 21) & 0x0FE00000)
#define AM_REG_OTP_INFO1_POWERSTATE3_TVRGCACTTRIM_Pos 21
#define AM_REG_OTP_INFO1_POWERSTATE3_TVRGCACTTRIM_Msk 0x0FE00000
#define AM_REG_OTP_INFO1_POWERSTATE3_CORELDOTEMPCOTRIM_S 17
#define AM_REG_OTP_INFO1_POWERSTATE3_CORELDOTEMPCOTRIM_M 0x001E0000
#define AM_REG_OTP_INFO1_POWERSTATE3_CORELDOTEMPCOTRIM(n) (((uint32_t)(n) << 17) & 0x001E0000)
#define AM_REG_OTP_INFO1_POWERSTATE3_CORELDOTEMPCOTRIM_Pos 17
#define AM_REG_OTP_INFO1_POWERSTATE3_CORELDOTEMPCOTRIM_Msk 0x001E0000
#define AM_REG_OTP_INFO1_POWERSTATE3_CORELDOACTTRIM_S 7
#define AM_REG_OTP_INFO1_POWERSTATE3_CORELDOACTTRIM_M 0x0001FF80
#define AM_REG_OTP_INFO1_POWERSTATE3_CORELDOACTTRIM(n) (((uint32_t)(n) << 7) & 0x0001FF80)
#define AM_REG_OTP_INFO1_POWERSTATE3_CORELDOACTTRIM_Pos 7
#define AM_REG_OTP_INFO1_POWERSTATE3_CORELDOACTTRIM_Msk 0x0001FF80
#define AM_REG_OTP_INFO1_POWERSTATE3_TVRGFACTTRIM_S 0
#define AM_REG_OTP_INFO1_POWERSTATE3_TVRGFACTTRIM_M 0x0000007F
#define AM_REG_OTP_INFO1_POWERSTATE3_TVRGFACTTRIM(n) (((uint32_t)(n) << 0) & 0x0000007F)
#define AM_REG_OTP_INFO1_POWERSTATE3_TVRGFACTTRIM_Pos 0
#define AM_REG_OTP_INFO1_POWERSTATE3_TVRGFACTTRIM_Msk 0x0000007F

// POWERSTATE4 - Power state register. CPU LP mode, GPU on and/or XYZ peripherals on. Temperature range greater than 50C.
#define AM_REG_OTP_INFO1_POWERSTATE4_RESVD29_S 29
#define AM_REG_OTP_INFO1_POWERSTATE4_RESVD29_M 0xE0000000
#define AM_REG_OTP_INFO1_POWERSTATE4_RESVD29(n) (((uint32_t)(n) << 29) & 0xE0000000)
#define AM_REG_OTP_INFO1_POWERSTATE4_RESVD29_Pos 29
#define AM_REG_OTP_INFO1_POWERSTATE4_RESVD29_Msk 0xE0000000
#define AM_REG_OTP_INFO1_POWERSTATE4_TVRGCVREFSEL_S 28
#define AM_REG_OTP_INFO1_POWERSTATE4_TVRGCVREFSEL_M 0x10000000
#define AM_REG_OTP_INFO1_POWERSTATE4_TVRGCVREFSEL(n) (((uint32_t)(n) << 28) & 0x10000000)
#define AM_REG_OTP_INFO1_POWERSTATE4_TVRGCVREFSEL_Pos 28
#define AM_REG_OTP_INFO1_POWERSTATE4_TVRGCVREFSEL_Msk 0x10000000
#define AM_REG_OTP_INFO1_POWERSTATE4_TVRGCACTTRIM_S 21
#define AM_REG_OTP_INFO1_POWERSTATE4_TVRGCACTTRIM_M 0x0FE00000
#define AM_REG_OTP_INFO1_POWERSTATE4_TVRGCACTTRIM(n) (((uint32_t)(n) << 21) & 0x0FE00000)
#define AM_REG_OTP_INFO1_POWERSTATE4_TVRGCACTTRIM_Pos 21
#define AM_REG_OTP_INFO1_POWERSTATE4_TVRGCACTTRIM_Msk 0x0FE00000
#define AM_REG_OTP_INFO1_POWERSTATE4_CORELDOTEMPCOTRIM_S 17
#define AM_REG_OTP_INFO1_POWERSTATE4_CORELDOTEMPCOTRIM_M 0x001E0000
#define AM_REG_OTP_INFO1_POWERSTATE4_CORELDOTEMPCOTRIM(n) (((uint32_t)(n) << 17) & 0x001E0000)
#define AM_REG_OTP_INFO1_POWERSTATE4_CORELDOTEMPCOTRIM_Pos 17
#define AM_REG_OTP_INFO1_POWERSTATE4_CORELDOTEMPCOTRIM_Msk 0x001E0000
#define AM_REG_OTP_INFO1_POWERSTATE4_CORELDOACTTRIM_S 7
#define AM_REG_OTP_INFO1_POWERSTATE4_CORELDOACTTRIM_M 0x0001FF80
#define AM_REG_OTP_INFO1_POWERSTATE4_CORELDOACTTRIM(n) (((uint32_t)(n) << 7) & 0x0001FF80)
#define AM_REG_OTP_INFO1_POWERSTATE4_CORELDOACTTRIM_Pos 7
#define AM_REG_OTP_INFO1_POWERSTATE4_CORELDOACTTRIM_Msk 0x0001FF80
#define AM_REG_OTP_INFO1_POWERSTATE4_TVRGFACTTRIM_S 0
#define AM_REG_OTP_INFO1_POWERSTATE4_TVRGFACTTRIM_M 0x0000007F
#define AM_REG_OTP_INFO1_POWERSTATE4_TVRGFACTTRIM(n) (((uint32_t)(n) << 0) & 0x0000007F)
#define AM_REG_OTP_INFO1_POWERSTATE4_TVRGFACTTRIM_Pos 0
#define AM_REG_OTP_INFO1_POWERSTATE4_TVRGFACTTRIM_Msk 0x0000007F

// POWERSTATE5 - Power state register. CPU LP mode, GPU on and/or XYZ peripherals on. Temperature range 0C to 50C.
#define AM_REG_OTP_INFO1_POWERSTATE5_RESVD29_S 29
#define AM_REG_OTP_INFO1_POWERSTATE5_RESVD29_M 0xE0000000
#define AM_REG_OTP_INFO1_POWERSTATE5_RESVD29(n) (((uint32_t)(n) << 29) & 0xE0000000)
#define AM_REG_OTP_INFO1_POWERSTATE5_RESVD29_Pos 29
#define AM_REG_OTP_INFO1_POWERSTATE5_RESVD29_Msk 0xE0000000
#define AM_REG_OTP_INFO1_POWERSTATE5_TVRGCVREFSEL_S 28
#define AM_REG_OTP_INFO1_POWERSTATE5_TVRGCVREFSEL_M 0x10000000
#define AM_REG_OTP_INFO1_POWERSTATE5_TVRGCVREFSEL(n) (((uint32_t)(n) << 28) & 0x10000000)
#define AM_REG_OTP_INFO1_POWERSTATE5_TVRGCVREFSEL_Pos 28
#define AM_REG_OTP_INFO1_POWERSTATE5_TVRGCVREFSEL_Msk 0x10000000
#define AM_REG_OTP_INFO1_POWERSTATE5_TVRGCACTTRIM_S 21
#define AM_REG_OTP_INFO1_POWERSTATE5_TVRGCACTTRIM_M 0x0FE00000
#define AM_REG_OTP_INFO1_POWERSTATE5_TVRGCACTTRIM(n) (((uint32_t)(n) << 21) & 0x0FE00000)
#define AM_REG_OTP_INFO1_POWERSTATE5_TVRGCACTTRIM_Pos 21
#define AM_REG_OTP_INFO1_POWERSTATE5_TVRGCACTTRIM_Msk 0x0FE00000
#define AM_REG_OTP_INFO1_POWERSTATE5_CORELDOTEMPCOTRIM_S 17
#define AM_REG_OTP_INFO1_POWERSTATE5_CORELDOTEMPCOTRIM_M 0x001E0000
#define AM_REG_OTP_INFO1_POWERSTATE5_CORELDOTEMPCOTRIM(n) (((uint32_t)(n) << 17) & 0x001E0000)
#define AM_REG_OTP_INFO1_POWERSTATE5_CORELDOTEMPCOTRIM_Pos 17
#define AM_REG_OTP_INFO1_POWERSTATE5_CORELDOTEMPCOTRIM_Msk 0x001E0000
#define AM_REG_OTP_INFO1_POWERSTATE5_CORELDOACTTRIM_S 7
#define AM_REG_OTP_INFO1_POWERSTATE5_CORELDOACTTRIM_M 0x0001FF80
#define AM_REG_OTP_INFO1_POWERSTATE5_CORELDOACTTRIM(n) (((uint32_t)(n) << 7) & 0x0001FF80)
#define AM_REG_OTP_INFO1_POWERSTATE5_CORELDOACTTRIM_Pos 7
#define AM_REG_OTP_INFO1_POWERSTATE5_CORELDOACTTRIM_Msk 0x0001FF80
#define AM_REG_OTP_INFO1_POWERSTATE5_TVRGFACTTRIM_S 0
#define AM_REG_OTP_INFO1_POWERSTATE5_TVRGFACTTRIM_M 0x0000007F
#define AM_REG_OTP_INFO1_POWERSTATE5_TVRGFACTTRIM(n) (((uint32_t)(n) << 0) & 0x0000007F)
#define AM_REG_OTP_INFO1_POWERSTATE5_TVRGFACTTRIM_Pos 0
#define AM_REG_OTP_INFO1_POWERSTATE5_TVRGFACTTRIM_Msk 0x0000007F

// POWERSTATE6 - Power state register. CPU LP mode, GPU on and/or XYZ peripherals on Temperature range -20C to 0C.
#define AM_REG_OTP_INFO1_POWERSTATE6_RESVD29_S 29
#define AM_REG_OTP_INFO1_POWERSTATE6_RESVD29_M 0xE0000000
#define AM_REG_OTP_INFO1_POWERSTATE6_RESVD29(n) (((uint32_t)(n) << 29) & 0xE0000000)
#define AM_REG_OTP_INFO1_POWERSTATE6_RESVD29_Pos 29
#define AM_REG_OTP_INFO1_POWERSTATE6_RESVD29_Msk 0xE0000000
#define AM_REG_OTP_INFO1_POWERSTATE6_TVRGCVREFSEL_S 28
#define AM_REG_OTP_INFO1_POWERSTATE6_TVRGCVREFSEL_M 0x10000000
#define AM_REG_OTP_INFO1_POWERSTATE6_TVRGCVREFSEL(n) (((uint32_t)(n) << 28) & 0x10000000)
#define AM_REG_OTP_INFO1_POWERSTATE6_TVRGCVREFSEL_Pos 28
#define AM_REG_OTP_INFO1_POWERSTATE6_TVRGCVREFSEL_Msk 0x10000000
#define AM_REG_OTP_INFO1_POWERSTATE6_TVRGCACTTRIM_S 21
#define AM_REG_OTP_INFO1_POWERSTATE6_TVRGCACTTRIM_M 0x0FE00000
#define AM_REG_OTP_INFO1_POWERSTATE6_TVRGCACTTRIM(n) (((uint32_t)(n) << 21) & 0x0FE00000)
#define AM_REG_OTP_INFO1_POWERSTATE6_TVRGCACTTRIM_Pos 21
#define AM_REG_OTP_INFO1_POWERSTATE6_TVRGCACTTRIM_Msk 0x0FE00000
#define AM_REG_OTP_INFO1_POWERSTATE6_CORELDOTEMPCOTRIM_S 17
#define AM_REG_OTP_INFO1_POWERSTATE6_CORELDOTEMPCOTRIM_M 0x001E0000
#define AM_REG_OTP_INFO1_POWERSTATE6_CORELDOTEMPCOTRIM(n) (((uint32_t)(n) << 17) & 0x001E0000)
#define AM_REG_OTP_INFO1_POWERSTATE6_CORELDOTEMPCOTRIM_Pos 17
#define AM_REG_OTP_INFO1_POWERSTATE6_CORELDOTEMPCOTRIM_Msk 0x001E0000
#define AM_REG_OTP_INFO1_POWERSTATE6_CORELDOACTTRIM_S 7
#define AM_REG_OTP_INFO1_POWERSTATE6_CORELDOACTTRIM_M 0x0001FF80
#define AM_REG_OTP_INFO1_POWERSTATE6_CORELDOACTTRIM(n) (((uint32_t)(n) << 7) & 0x0001FF80)
#define AM_REG_OTP_INFO1_POWERSTATE6_CORELDOACTTRIM_Pos 7
#define AM_REG_OTP_INFO1_POWERSTATE6_CORELDOACTTRIM_Msk 0x0001FF80
#define AM_REG_OTP_INFO1_POWERSTATE6_TVRGFACTTRIM_S 0
#define AM_REG_OTP_INFO1_POWERSTATE6_TVRGFACTTRIM_M 0x0000007F
#define AM_REG_OTP_INFO1_POWERSTATE6_TVRGFACTTRIM(n) (((uint32_t)(n) << 0) & 0x0000007F)
#define AM_REG_OTP_INFO1_POWERSTATE6_TVRGFACTTRIM_Pos 0
#define AM_REG_OTP_INFO1_POWERSTATE6_TVRGFACTTRIM_Msk 0x0000007F

// POWERSTATE7 - Power state register. CPU LP mode, GPU on and/or XYZ peripherals on. Temperature range -40C to -20C.
#define AM_REG_OTP_INFO1_POWERSTATE7_RESVD29_S 29
#define AM_REG_OTP_INFO1_POWERSTATE7_RESVD29_M 0xE0000000
#define AM_REG_OTP_INFO1_POWERSTATE7_RESVD29(n) (((uint32_t)(n) << 29) & 0xE0000000)
#define AM_REG_OTP_INFO1_POWERSTATE7_RESVD29_Pos 29
#define AM_REG_OTP_INFO1_POWERSTATE7_RESVD29_Msk 0xE0000000
#define AM_REG_OTP_INFO1_POWERSTATE7_TVRGCVREFSEL_S 28
#define AM_REG_OTP_INFO1_POWERSTATE7_TVRGCVREFSEL_M 0x10000000
#define AM_REG_OTP_INFO1_POWERSTATE7_TVRGCVREFSEL(n) (((uint32_t)(n) << 28) & 0x10000000)
#define AM_REG_OTP_INFO1_POWERSTATE7_TVRGCVREFSEL_Pos 28
#define AM_REG_OTP_INFO1_POWERSTATE7_TVRGCVREFSEL_Msk 0x10000000
#define AM_REG_OTP_INFO1_POWERSTATE7_TVRGCACTTRIM_S 21
#define AM_REG_OTP_INFO1_POWERSTATE7_TVRGCACTTRIM_M 0x0FE00000
#define AM_REG_OTP_INFO1_POWERSTATE7_TVRGCACTTRIM(n) (((uint32_t)(n) << 21) & 0x0FE00000)
#define AM_REG_OTP_INFO1_POWERSTATE7_TVRGCACTTRIM_Pos 21
#define AM_REG_OTP_INFO1_POWERSTATE7_TVRGCACTTRIM_Msk 0x0FE00000
#define AM_REG_OTP_INFO1_POWERSTATE7_CORELDOTEMPCOTRIM_S 17
#define AM_REG_OTP_INFO1_POWERSTATE7_CORELDOTEMPCOTRIM_M 0x001E0000
#define AM_REG_OTP_INFO1_POWERSTATE7_CORELDOTEMPCOTRIM(n) (((uint32_t)(n) << 17) & 0x001E0000)
#define AM_REG_OTP_INFO1_POWERSTATE7_CORELDOTEMPCOTRIM_Pos 17
#define AM_REG_OTP_INFO1_POWERSTATE7_CORELDOTEMPCOTRIM_Msk 0x001E0000
#define AM_REG_OTP_INFO1_POWERSTATE7_CORELDOACTTRIM_S 7
#define AM_REG_OTP_INFO1_POWERSTATE7_CORELDOACTTRIM_M 0x0001FF80
#define AM_REG_OTP_INFO1_POWERSTATE7_CORELDOACTTRIM(n) (((uint32_t)(n) << 7) & 0x0001FF80)
#define AM_REG_OTP_INFO1_POWERSTATE7_CORELDOACTTRIM_Pos 7
#define AM_REG_OTP_INFO1_POWERSTATE7_CORELDOACTTRIM_Msk 0x0001FF80
#define AM_REG_OTP_INFO1_POWERSTATE7_TVRGFACTTRIM_S 0
#define AM_REG_OTP_INFO1_POWERSTATE7_TVRGFACTTRIM_M 0x0000007F
#define AM_REG_OTP_INFO1_POWERSTATE7_TVRGFACTTRIM(n) (((uint32_t)(n) << 0) & 0x0000007F)
#define AM_REG_OTP_INFO1_POWERSTATE7_TVRGFACTTRIM_Pos 0
#define AM_REG_OTP_INFO1_POWERSTATE7_TVRGFACTTRIM_Msk 0x0000007F

// POWERSTATE8 - Power state register. CPU HP mode, GPU off, XYZ peripherals off. Temperature range greater than 50C.
#define AM_REG_OTP_INFO1_POWERSTATE8_RESVD29_S 29
#define AM_REG_OTP_INFO1_POWERSTATE8_RESVD29_M 0xE0000000
#define AM_REG_OTP_INFO1_POWERSTATE8_RESVD29(n) (((uint32_t)(n) << 29) & 0xE0000000)
#define AM_REG_OTP_INFO1_POWERSTATE8_RESVD29_Pos 29
#define AM_REG_OTP_INFO1_POWERSTATE8_RESVD29_Msk 0xE0000000
#define AM_REG_OTP_INFO1_POWERSTATE8_TVRGCVREFSEL_S 28
#define AM_REG_OTP_INFO1_POWERSTATE8_TVRGCVREFSEL_M 0x10000000
#define AM_REG_OTP_INFO1_POWERSTATE8_TVRGCVREFSEL(n) (((uint32_t)(n) << 28) & 0x10000000)
#define AM_REG_OTP_INFO1_POWERSTATE8_TVRGCVREFSEL_Pos 28
#define AM_REG_OTP_INFO1_POWERSTATE8_TVRGCVREFSEL_Msk 0x10000000
#define AM_REG_OTP_INFO1_POWERSTATE8_TVRGCACTTRIM_S 21
#define AM_REG_OTP_INFO1_POWERSTATE8_TVRGCACTTRIM_M 0x0FE00000
#define AM_REG_OTP_INFO1_POWERSTATE8_TVRGCACTTRIM(n) (((uint32_t)(n) << 21) & 0x0FE00000)
#define AM_REG_OTP_INFO1_POWERSTATE8_TVRGCACTTRIM_Pos 21
#define AM_REG_OTP_INFO1_POWERSTATE8_TVRGCACTTRIM_Msk 0x0FE00000
#define AM_REG_OTP_INFO1_POWERSTATE8_CORELDOTEMPCOTRIM_S 17
#define AM_REG_OTP_INFO1_POWERSTATE8_CORELDOTEMPCOTRIM_M 0x001E0000
#define AM_REG_OTP_INFO1_POWERSTATE8_CORELDOTEMPCOTRIM(n) (((uint32_t)(n) << 17) & 0x001E0000)
#define AM_REG_OTP_INFO1_POWERSTATE8_CORELDOTEMPCOTRIM_Pos 17
#define AM_REG_OTP_INFO1_POWERSTATE8_CORELDOTEMPCOTRIM_Msk 0x001E0000
#define AM_REG_OTP_INFO1_POWERSTATE8_CORELDOACTTRIM_S 7
#define AM_REG_OTP_INFO1_POWERSTATE8_CORELDOACTTRIM_M 0x0001FF80
#define AM_REG_OTP_INFO1_POWERSTATE8_CORELDOACTTRIM(n) (((uint32_t)(n) << 7) & 0x0001FF80)
#define AM_REG_OTP_INFO1_POWERSTATE8_CORELDOACTTRIM_Pos 7
#define AM_REG_OTP_INFO1_POWERSTATE8_CORELDOACTTRIM_Msk 0x0001FF80
#define AM_REG_OTP_INFO1_POWERSTATE8_TVRGFACTTRIM_S 0
#define AM_REG_OTP_INFO1_POWERSTATE8_TVRGFACTTRIM_M 0x0000007F
#define AM_REG_OTP_INFO1_POWERSTATE8_TVRGFACTTRIM(n) (((uint32_t)(n) << 0) & 0x0000007F)
#define AM_REG_OTP_INFO1_POWERSTATE8_TVRGFACTTRIM_Pos 0
#define AM_REG_OTP_INFO1_POWERSTATE8_TVRGFACTTRIM_Msk 0x0000007F

// POWERSTATE9 - Power state register. CPU HP mode, GPU off, XYZ peripherals off. Temperature range 0C to 50C.
#define AM_REG_OTP_INFO1_POWERSTATE9_RESVD29_S 29
#define AM_REG_OTP_INFO1_POWERSTATE9_RESVD29_M 0xE0000000
#define AM_REG_OTP_INFO1_POWERSTATE9_RESVD29(n) (((uint32_t)(n) << 29) & 0xE0000000)
#define AM_REG_OTP_INFO1_POWERSTATE9_RESVD29_Pos 29
#define AM_REG_OTP_INFO1_POWERSTATE9_RESVD29_Msk 0xE0000000
#define AM_REG_OTP_INFO1_POWERSTATE9_TVRGCVREFSEL_S 28
#define AM_REG_OTP_INFO1_POWERSTATE9_TVRGCVREFSEL_M 0x10000000
#define AM_REG_OTP_INFO1_POWERSTATE9_TVRGCVREFSEL(n) (((uint32_t)(n) << 28) & 0x10000000)
#define AM_REG_OTP_INFO1_POWERSTATE9_TVRGCVREFSEL_Pos 28
#define AM_REG_OTP_INFO1_POWERSTATE9_TVRGCVREFSEL_Msk 0x10000000
#define AM_REG_OTP_INFO1_POWERSTATE9_TVRGCACTTRIM_S 21
#define AM_REG_OTP_INFO1_POWERSTATE9_TVRGCACTTRIM_M 0x0FE00000
#define AM_REG_OTP_INFO1_POWERSTATE9_TVRGCACTTRIM(n) (((uint32_t)(n) << 21) & 0x0FE00000)
#define AM_REG_OTP_INFO1_POWERSTATE9_TVRGCACTTRIM_Pos 21
#define AM_REG_OTP_INFO1_POWERSTATE9_TVRGCACTTRIM_Msk 0x0FE00000
#define AM_REG_OTP_INFO1_POWERSTATE9_CORELDOTEMPCOTRIM_S 17
#define AM_REG_OTP_INFO1_POWERSTATE9_CORELDOTEMPCOTRIM_M 0x001E0000
#define AM_REG_OTP_INFO1_POWERSTATE9_CORELDOTEMPCOTRIM(n) (((uint32_t)(n) << 17) & 0x001E0000)
#define AM_REG_OTP_INFO1_POWERSTATE9_CORELDOTEMPCOTRIM_Pos 17
#define AM_REG_OTP_INFO1_POWERSTATE9_CORELDOTEMPCOTRIM_Msk 0x001E0000
#define AM_REG_OTP_INFO1_POWERSTATE9_CORELDOACTTRIM_S 7
#define AM_REG_OTP_INFO1_POWERSTATE9_CORELDOACTTRIM_M 0x0001FF80
#define AM_REG_OTP_INFO1_POWERSTATE9_CORELDOACTTRIM(n) (((uint32_t)(n) << 7) & 0x0001FF80)
#define AM_REG_OTP_INFO1_POWERSTATE9_CORELDOACTTRIM_Pos 7
#define AM_REG_OTP_INFO1_POWERSTATE9_CORELDOACTTRIM_Msk 0x0001FF80
#define AM_REG_OTP_INFO1_POWERSTATE9_TVRGFACTTRIM_S 0
#define AM_REG_OTP_INFO1_POWERSTATE9_TVRGFACTTRIM_M 0x0000007F
#define AM_REG_OTP_INFO1_POWERSTATE9_TVRGFACTTRIM(n) (((uint32_t)(n) << 0) & 0x0000007F)
#define AM_REG_OTP_INFO1_POWERSTATE9_TVRGFACTTRIM_Pos 0
#define AM_REG_OTP_INFO1_POWERSTATE9_TVRGFACTTRIM_Msk 0x0000007F

// POWERSTATE10 - Power state register. CPU HP mode, GPU off, XYZ peripherals off. Temperature range -20C to 0C.
#define AM_REG_OTP_INFO1_POWERSTATE10_RESVD29_S 29
#define AM_REG_OTP_INFO1_POWERSTATE10_RESVD29_M 0xE0000000
#define AM_REG_OTP_INFO1_POWERSTATE10_RESVD29(n) (((uint32_t)(n) << 29) & 0xE0000000)
#define AM_REG_OTP_INFO1_POWERSTATE10_RESVD29_Pos 29
#define AM_REG_OTP_INFO1_POWERSTATE10_RESVD29_Msk 0xE0000000
#define AM_REG_OTP_INFO1_POWERSTATE10_TVRGCVREFSEL_S 28
#define AM_REG_OTP_INFO1_POWERSTATE10_TVRGCVREFSEL_M 0x10000000
#define AM_REG_OTP_INFO1_POWERSTATE10_TVRGCVREFSEL(n) (((uint32_t)(n) << 28) & 0x10000000)
#define AM_REG_OTP_INFO1_POWERSTATE10_TVRGCVREFSEL_Pos 28
#define AM_REG_OTP_INFO1_POWERSTATE10_TVRGCVREFSEL_Msk 0x10000000
#define AM_REG_OTP_INFO1_POWERSTATE10_TVRGCACTTRIM_S 21
#define AM_REG_OTP_INFO1_POWERSTATE10_TVRGCACTTRIM_M 0x0FE00000
#define AM_REG_OTP_INFO1_POWERSTATE10_TVRGCACTTRIM(n) (((uint32_t)(n) << 21) & 0x0FE00000)
#define AM_REG_OTP_INFO1_POWERSTATE10_TVRGCACTTRIM_Pos 21
#define AM_REG_OTP_INFO1_POWERSTATE10_TVRGCACTTRIM_Msk 0x0FE00000
#define AM_REG_OTP_INFO1_POWERSTATE10_CORELDOTEMPCOTRIM_S 17
#define AM_REG_OTP_INFO1_POWERSTATE10_CORELDOTEMPCOTRIM_M 0x001E0000
#define AM_REG_OTP_INFO1_POWERSTATE10_CORELDOTEMPCOTRIM(n) (((uint32_t)(n) << 17) & 0x001E0000)
#define AM_REG_OTP_INFO1_POWERSTATE10_CORELDOTEMPCOTRIM_Pos 17
#define AM_REG_OTP_INFO1_POWERSTATE10_CORELDOTEMPCOTRIM_Msk 0x001E0000
#define AM_REG_OTP_INFO1_POWERSTATE10_CORELDOACTTRIM_S 7
#define AM_REG_OTP_INFO1_POWERSTATE10_CORELDOACTTRIM_M 0x0001FF80
#define AM_REG_OTP_INFO1_POWERSTATE10_CORELDOACTTRIM(n) (((uint32_t)(n) << 7) & 0x0001FF80)
#define AM_REG_OTP_INFO1_POWERSTATE10_CORELDOACTTRIM_Pos 7
#define AM_REG_OTP_INFO1_POWERSTATE10_CORELDOACTTRIM_Msk 0x0001FF80
#define AM_REG_OTP_INFO1_POWERSTATE10_TVRGFACTTRIM_S 0
#define AM_REG_OTP_INFO1_POWERSTATE10_TVRGFACTTRIM_M 0x0000007F
#define AM_REG_OTP_INFO1_POWERSTATE10_TVRGFACTTRIM(n) (((uint32_t)(n) << 0) & 0x0000007F)
#define AM_REG_OTP_INFO1_POWERSTATE10_TVRGFACTTRIM_Pos 0
#define AM_REG_OTP_INFO1_POWERSTATE10_TVRGFACTTRIM_Msk 0x0000007F

// POWERSTATE11 - Power state register. CPU HP mode, GPU off, XYZ peripherals off. Temperature range -40C to -20C.
#define AM_REG_OTP_INFO1_POWERSTATE11_RESVD29_S 29
#define AM_REG_OTP_INFO1_POWERSTATE11_RESVD29_M 0xE0000000
#define AM_REG_OTP_INFO1_POWERSTATE11_RESVD29(n) (((uint32_t)(n) << 29) & 0xE0000000)
#define AM_REG_OTP_INFO1_POWERSTATE11_RESVD29_Pos 29
#define AM_REG_OTP_INFO1_POWERSTATE11_RESVD29_Msk 0xE0000000
#define AM_REG_OTP_INFO1_POWERSTATE11_TVRGCVREFSEL_S 28
#define AM_REG_OTP_INFO1_POWERSTATE11_TVRGCVREFSEL_M 0x10000000
#define AM_REG_OTP_INFO1_POWERSTATE11_TVRGCVREFSEL(n) (((uint32_t)(n) << 28) & 0x10000000)
#define AM_REG_OTP_INFO1_POWERSTATE11_TVRGCVREFSEL_Pos 28
#define AM_REG_OTP_INFO1_POWERSTATE11_TVRGCVREFSEL_Msk 0x10000000
#define AM_REG_OTP_INFO1_POWERSTATE11_TVRGCACTTRIM_S 21
#define AM_REG_OTP_INFO1_POWERSTATE11_TVRGCACTTRIM_M 0x0FE00000
#define AM_REG_OTP_INFO1_POWERSTATE11_TVRGCACTTRIM(n) (((uint32_t)(n) << 21) & 0x0FE00000)
#define AM_REG_OTP_INFO1_POWERSTATE11_TVRGCACTTRIM_Pos 21
#define AM_REG_OTP_INFO1_POWERSTATE11_TVRGCACTTRIM_Msk 0x0FE00000
#define AM_REG_OTP_INFO1_POWERSTATE11_CORELDOTEMPCOTRIM_S 17
#define AM_REG_OTP_INFO1_POWERSTATE11_CORELDOTEMPCOTRIM_M 0x001E0000
#define AM_REG_OTP_INFO1_POWERSTATE11_CORELDOTEMPCOTRIM(n) (((uint32_t)(n) << 17) & 0x001E0000)
#define AM_REG_OTP_INFO1_POWERSTATE11_CORELDOTEMPCOTRIM_Pos 17
#define AM_REG_OTP_INFO1_POWERSTATE11_CORELDOTEMPCOTRIM_Msk 0x001E0000
#define AM_REG_OTP_INFO1_POWERSTATE11_CORELDOACTTRIM_S 7
#define AM_REG_OTP_INFO1_POWERSTATE11_CORELDOACTTRIM_M 0x0001FF80
#define AM_REG_OTP_INFO1_POWERSTATE11_CORELDOACTTRIM(n) (((uint32_t)(n) << 7) & 0x0001FF80)
#define AM_REG_OTP_INFO1_POWERSTATE11_CORELDOACTTRIM_Pos 7
#define AM_REG_OTP_INFO1_POWERSTATE11_CORELDOACTTRIM_Msk 0x0001FF80
#define AM_REG_OTP_INFO1_POWERSTATE11_TVRGFACTTRIM_S 0
#define AM_REG_OTP_INFO1_POWERSTATE11_TVRGFACTTRIM_M 0x0000007F
#define AM_REG_OTP_INFO1_POWERSTATE11_TVRGFACTTRIM(n) (((uint32_t)(n) << 0) & 0x0000007F)
#define AM_REG_OTP_INFO1_POWERSTATE11_TVRGFACTTRIM_Pos 0
#define AM_REG_OTP_INFO1_POWERSTATE11_TVRGFACTTRIM_Msk 0x0000007F

// POWERSTATE12 - Power state register. CPU HP mode, GPU on and/or XYZ peripherals on. Temperature range greater than 50C.
#define AM_REG_OTP_INFO1_POWERSTATE12_RESVD29_S 29
#define AM_REG_OTP_INFO1_POWERSTATE12_RESVD29_M 0xE0000000
#define AM_REG_OTP_INFO1_POWERSTATE12_RESVD29(n) (((uint32_t)(n) << 29) & 0xE0000000)
#define AM_REG_OTP_INFO1_POWERSTATE12_RESVD29_Pos 29
#define AM_REG_OTP_INFO1_POWERSTATE12_RESVD29_Msk 0xE0000000
#define AM_REG_OTP_INFO1_POWERSTATE12_TVRGCVREFSEL_S 28
#define AM_REG_OTP_INFO1_POWERSTATE12_TVRGCVREFSEL_M 0x10000000
#define AM_REG_OTP_INFO1_POWERSTATE12_TVRGCVREFSEL(n) (((uint32_t)(n) << 28) & 0x10000000)
#define AM_REG_OTP_INFO1_POWERSTATE12_TVRGCVREFSEL_Pos 28
#define AM_REG_OTP_INFO1_POWERSTATE12_TVRGCVREFSEL_Msk 0x10000000
#define AM_REG_OTP_INFO1_POWERSTATE12_TVRGCACTTRIM_S 21
#define AM_REG_OTP_INFO1_POWERSTATE12_TVRGCACTTRIM_M 0x0FE00000
#define AM_REG_OTP_INFO1_POWERSTATE12_TVRGCACTTRIM(n) (((uint32_t)(n) << 21) & 0x0FE00000)
#define AM_REG_OTP_INFO1_POWERSTATE12_TVRGCACTTRIM_Pos 21
#define AM_REG_OTP_INFO1_POWERSTATE12_TVRGCACTTRIM_Msk 0x0FE00000
#define AM_REG_OTP_INFO1_POWERSTATE12_CORELDOTEMPCOTRIM_S 17
#define AM_REG_OTP_INFO1_POWERSTATE12_CORELDOTEMPCOTRIM_M 0x001E0000
#define AM_REG_OTP_INFO1_POWERSTATE12_CORELDOTEMPCOTRIM(n) (((uint32_t)(n) << 17) & 0x001E0000)
#define AM_REG_OTP_INFO1_POWERSTATE12_CORELDOTEMPCOTRIM_Pos 17
#define AM_REG_OTP_INFO1_POWERSTATE12_CORELDOTEMPCOTRIM_Msk 0x001E0000
#define AM_REG_OTP_INFO1_POWERSTATE12_CORELDOACTTRIM_S 7
#define AM_REG_OTP_INFO1_POWERSTATE12_CORELDOACTTRIM_M 0x0001FF80
#define AM_REG_OTP_INFO1_POWERSTATE12_CORELDOACTTRIM(n) (((uint32_t)(n) << 7) & 0x0001FF80)
#define AM_REG_OTP_INFO1_POWERSTATE12_CORELDOACTTRIM_Pos 7
#define AM_REG_OTP_INFO1_POWERSTATE12_CORELDOACTTRIM_Msk 0x0001FF80
#define AM_REG_OTP_INFO1_POWERSTATE12_TVRGFACTTRIM_S 0
#define AM_REG_OTP_INFO1_POWERSTATE12_TVRGFACTTRIM_M 0x0000007F
#define AM_REG_OTP_INFO1_POWERSTATE12_TVRGFACTTRIM(n) (((uint32_t)(n) << 0) & 0x0000007F)
#define AM_REG_OTP_INFO1_POWERSTATE12_TVRGFACTTRIM_Pos 0
#define AM_REG_OTP_INFO1_POWERSTATE12_TVRGFACTTRIM_Msk 0x0000007F

// POWERSTATE13 - Power state register. CPU HP mode, GPU on and/or XYZ peripherals on. Temperature range 0C to 50C.
#define AM_REG_OTP_INFO1_POWERSTATE13_RESVD29_S 29
#define AM_REG_OTP_INFO1_POWERSTATE13_RESVD29_M 0xE0000000
#define AM_REG_OTP_INFO1_POWERSTATE13_RESVD29(n) (((uint32_t)(n) << 29) & 0xE0000000)
#define AM_REG_OTP_INFO1_POWERSTATE13_RESVD29_Pos 29
#define AM_REG_OTP_INFO1_POWERSTATE13_RESVD29_Msk 0xE0000000
#define AM_REG_OTP_INFO1_POWERSTATE13_TVRGCVREFSEL_S 28
#define AM_REG_OTP_INFO1_POWERSTATE13_TVRGCVREFSEL_M 0x10000000
#define AM_REG_OTP_INFO1_POWERSTATE13_TVRGCVREFSEL(n) (((uint32_t)(n) << 28) & 0x10000000)
#define AM_REG_OTP_INFO1_POWERSTATE13_TVRGCVREFSEL_Pos 28
#define AM_REG_OTP_INFO1_POWERSTATE13_TVRGCVREFSEL_Msk 0x10000000
#define AM_REG_OTP_INFO1_POWERSTATE13_TVRGCACTTRIM_S 21
#define AM_REG_OTP_INFO1_POWERSTATE13_TVRGCACTTRIM_M 0x0FE00000
#define AM_REG_OTP_INFO1_POWERSTATE13_TVRGCACTTRIM(n) (((uint32_t)(n) << 21) & 0x0FE00000)
#define AM_REG_OTP_INFO1_POWERSTATE13_TVRGCACTTRIM_Pos 21
#define AM_REG_OTP_INFO1_POWERSTATE13_TVRGCACTTRIM_Msk 0x0FE00000
#define AM_REG_OTP_INFO1_POWERSTATE13_CORELDOTEMPCOTRIM_S 17
#define AM_REG_OTP_INFO1_POWERSTATE13_CORELDOTEMPCOTRIM_M 0x001E0000
#define AM_REG_OTP_INFO1_POWERSTATE13_CORELDOTEMPCOTRIM(n) (((uint32_t)(n) << 17) & 0x001E0000)
#define AM_REG_OTP_INFO1_POWERSTATE13_CORELDOTEMPCOTRIM_Pos 17
#define AM_REG_OTP_INFO1_POWERSTATE13_CORELDOTEMPCOTRIM_Msk 0x001E0000
#define AM_REG_OTP_INFO1_POWERSTATE13_CORELDOACTTRIM_S 7
#define AM_REG_OTP_INFO1_POWERSTATE13_CORELDOACTTRIM_M 0x0001FF80
#define AM_REG_OTP_INFO1_POWERSTATE13_CORELDOACTTRIM(n) (((uint32_t)(n) << 7) & 0x0001FF80)
#define AM_REG_OTP_INFO1_POWERSTATE13_CORELDOACTTRIM_Pos 7
#define AM_REG_OTP_INFO1_POWERSTATE13_CORELDOACTTRIM_Msk 0x0001FF80
#define AM_REG_OTP_INFO1_POWERSTATE13_TVRGFACTTRIM_S 0
#define AM_REG_OTP_INFO1_POWERSTATE13_TVRGFACTTRIM_M 0x0000007F
#define AM_REG_OTP_INFO1_POWERSTATE13_TVRGFACTTRIM(n) (((uint32_t)(n) << 0) & 0x0000007F)
#define AM_REG_OTP_INFO1_POWERSTATE13_TVRGFACTTRIM_Pos 0
#define AM_REG_OTP_INFO1_POWERSTATE13_TVRGFACTTRIM_Msk 0x0000007F

// POWERSTATE14 - Power state register. CPU HP mode, GPU on and/or XYZ peripherals on. Temperature range -20C to 0C.
#define AM_REG_OTP_INFO1_POWERSTATE14_RESVD29_S 29
#define AM_REG_OTP_INFO1_POWERSTATE14_RESVD29_M 0xE0000000
#define AM_REG_OTP_INFO1_POWERSTATE14_RESVD29(n) (((uint32_t)(n) << 29) & 0xE0000000)
#define AM_REG_OTP_INFO1_POWERSTATE14_RESVD29_Pos 29
#define AM_REG_OTP_INFO1_POWERSTATE14_RESVD29_Msk 0xE0000000
#define AM_REG_OTP_INFO1_POWERSTATE14_TVRGCVREFSEL_S 28
#define AM_REG_OTP_INFO1_POWERSTATE14_TVRGCVREFSEL_M 0x10000000
#define AM_REG_OTP_INFO1_POWERSTATE14_TVRGCVREFSEL(n) (((uint32_t)(n) << 28) & 0x10000000)
#define AM_REG_OTP_INFO1_POWERSTATE14_TVRGCVREFSEL_Pos 28
#define AM_REG_OTP_INFO1_POWERSTATE14_TVRGCVREFSEL_Msk 0x10000000
#define AM_REG_OTP_INFO1_POWERSTATE14_TVRGCACTTRIM_S 21
#define AM_REG_OTP_INFO1_POWERSTATE14_TVRGCACTTRIM_M 0x0FE00000
#define AM_REG_OTP_INFO1_POWERSTATE14_TVRGCACTTRIM(n) (((uint32_t)(n) << 21) & 0x0FE00000)
#define AM_REG_OTP_INFO1_POWERSTATE14_TVRGCACTTRIM_Pos 21
#define AM_REG_OTP_INFO1_POWERSTATE14_TVRGCACTTRIM_Msk 0x0FE00000
#define AM_REG_OTP_INFO1_POWERSTATE14_CORELDOTEMPCOTRIM_S 17
#define AM_REG_OTP_INFO1_POWERSTATE14_CORELDOTEMPCOTRIM_M 0x001E0000
#define AM_REG_OTP_INFO1_POWERSTATE14_CORELDOTEMPCOTRIM(n) (((uint32_t)(n) << 17) & 0x001E0000)
#define AM_REG_OTP_INFO1_POWERSTATE14_CORELDOTEMPCOTRIM_Pos 17
#define AM_REG_OTP_INFO1_POWERSTATE14_CORELDOTEMPCOTRIM_Msk 0x001E0000
#define AM_REG_OTP_INFO1_POWERSTATE14_CORELDOACTTRIM_S 7
#define AM_REG_OTP_INFO1_POWERSTATE14_CORELDOACTTRIM_M 0x0001FF80
#define AM_REG_OTP_INFO1_POWERSTATE14_CORELDOACTTRIM(n) (((uint32_t)(n) << 7) & 0x0001FF80)
#define AM_REG_OTP_INFO1_POWERSTATE14_CORELDOACTTRIM_Pos 7
#define AM_REG_OTP_INFO1_POWERSTATE14_CORELDOACTTRIM_Msk 0x0001FF80
#define AM_REG_OTP_INFO1_POWERSTATE14_TVRGFACTTRIM_S 0
#define AM_REG_OTP_INFO1_POWERSTATE14_TVRGFACTTRIM_M 0x0000007F
#define AM_REG_OTP_INFO1_POWERSTATE14_TVRGFACTTRIM(n) (((uint32_t)(n) << 0) & 0x0000007F)
#define AM_REG_OTP_INFO1_POWERSTATE14_TVRGFACTTRIM_Pos 0
#define AM_REG_OTP_INFO1_POWERSTATE14_TVRGFACTTRIM_Msk 0x0000007F

// POWERSTATE15 - Power state register. CPU HP mode, GPU on and/or XYZ peripherals on. Temperature range -40C to -20C.
#define AM_REG_OTP_INFO1_POWERSTATE15_RESVD29_S 29
#define AM_REG_OTP_INFO1_POWERSTATE15_RESVD29_M 0xE0000000
#define AM_REG_OTP_INFO1_POWERSTATE15_RESVD29(n) (((uint32_t)(n) << 29) & 0xE0000000)
#define AM_REG_OTP_INFO1_POWERSTATE15_RESVD29_Pos 29
#define AM_REG_OTP_INFO1_POWERSTATE15_RESVD29_Msk 0xE0000000
#define AM_REG_OTP_INFO1_POWERSTATE15_TVRGCVREFSEL_S 28
#define AM_REG_OTP_INFO1_POWERSTATE15_TVRGCVREFSEL_M 0x10000000
#define AM_REG_OTP_INFO1_POWERSTATE15_TVRGCVREFSEL(n) (((uint32_t)(n) << 28) & 0x10000000)
#define AM_REG_OTP_INFO1_POWERSTATE15_TVRGCVREFSEL_Pos 28
#define AM_REG_OTP_INFO1_POWERSTATE15_TVRGCVREFSEL_Msk 0x10000000
#define AM_REG_OTP_INFO1_POWERSTATE15_TVRGCACTTRIM_S 21
#define AM_REG_OTP_INFO1_POWERSTATE15_TVRGCACTTRIM_M 0x0FE00000
#define AM_REG_OTP_INFO1_POWERSTATE15_TVRGCACTTRIM(n) (((uint32_t)(n) << 21) & 0x0FE00000)
#define AM_REG_OTP_INFO1_POWERSTATE15_TVRGCACTTRIM_Pos 21
#define AM_REG_OTP_INFO1_POWERSTATE15_TVRGCACTTRIM_Msk 0x0FE00000
#define AM_REG_OTP_INFO1_POWERSTATE15_CORELDOTEMPCOTRIM_S 17
#define AM_REG_OTP_INFO1_POWERSTATE15_CORELDOTEMPCOTRIM_M 0x001E0000
#define AM_REG_OTP_INFO1_POWERSTATE15_CORELDOTEMPCOTRIM(n) (((uint32_t)(n) << 17) & 0x001E0000)
#define AM_REG_OTP_INFO1_POWERSTATE15_CORELDOTEMPCOTRIM_Pos 17
#define AM_REG_OTP_INFO1_POWERSTATE15_CORELDOTEMPCOTRIM_Msk 0x001E0000
#define AM_REG_OTP_INFO1_POWERSTATE15_CORELDOACTTRIM_S 7
#define AM_REG_OTP_INFO1_POWERSTATE15_CORELDOACTTRIM_M 0x0001FF80
#define AM_REG_OTP_INFO1_POWERSTATE15_CORELDOACTTRIM(n) (((uint32_t)(n) << 7) & 0x0001FF80)
#define AM_REG_OTP_INFO1_POWERSTATE15_CORELDOACTTRIM_Pos 7
#define AM_REG_OTP_INFO1_POWERSTATE15_CORELDOACTTRIM_Msk 0x0001FF80
#define AM_REG_OTP_INFO1_POWERSTATE15_TVRGFACTTRIM_S 0
#define AM_REG_OTP_INFO1_POWERSTATE15_TVRGFACTTRIM_M 0x0000007F
#define AM_REG_OTP_INFO1_POWERSTATE15_TVRGFACTTRIM(n) (((uint32_t)(n) << 0) & 0x0000007F)
#define AM_REG_OTP_INFO1_POWERSTATE15_TVRGFACTTRIM_Pos 0
#define AM_REG_OTP_INFO1_POWERSTATE15_TVRGFACTTRIM_Msk 0x0000007F

// POWERSTATE16 - Power state register. CPU LP mode, GPU or SDIO on, greater than 50C.
#define AM_REG_OTP_INFO1_POWERSTATE16_RESVD29_S 29
#define AM_REG_OTP_INFO1_POWERSTATE16_RESVD29_M 0xE0000000
#define AM_REG_OTP_INFO1_POWERSTATE16_RESVD29(n) (((uint32_t)(n) << 29) & 0xE0000000)
#define AM_REG_OTP_INFO1_POWERSTATE16_RESVD29_Pos 29
#define AM_REG_OTP_INFO1_POWERSTATE16_RESVD29_Msk 0xE0000000
#define AM_REG_OTP_INFO1_POWERSTATE16_TVRGCVREFSEL_S 28
#define AM_REG_OTP_INFO1_POWERSTATE16_TVRGCVREFSEL_M 0x10000000
#define AM_REG_OTP_INFO1_POWERSTATE16_TVRGCVREFSEL(n) (((uint32_t)(n) << 28) & 0x10000000)
#define AM_REG_OTP_INFO1_POWERSTATE16_TVRGCVREFSEL_Pos 28
#define AM_REG_OTP_INFO1_POWERSTATE16_TVRGCVREFSEL_Msk 0x10000000
#define AM_REG_OTP_INFO1_POWERSTATE16_TVRGCACTTRIM_S 21
#define AM_REG_OTP_INFO1_POWERSTATE16_TVRGCACTTRIM_M 0x0FE00000
#define AM_REG_OTP_INFO1_POWERSTATE16_TVRGCACTTRIM(n) (((uint32_t)(n) << 21) & 0x0FE00000)
#define AM_REG_OTP_INFO1_POWERSTATE16_TVRGCACTTRIM_Pos 21
#define AM_REG_OTP_INFO1_POWERSTATE16_TVRGCACTTRIM_Msk 0x0FE00000
#define AM_REG_OTP_INFO1_POWERSTATE16_CORELDOTEMPCOTRIM_S 17
#define AM_REG_OTP_INFO1_POWERSTATE16_CORELDOTEMPCOTRIM_M 0x001E0000
#define AM_REG_OTP_INFO1_POWERSTATE16_CORELDOTEMPCOTRIM(n) (((uint32_t)(n) << 17) & 0x001E0000)
#define AM_REG_OTP_INFO1_POWERSTATE16_CORELDOTEMPCOTRIM_Pos 17
#define AM_REG_OTP_INFO1_POWERSTATE16_CORELDOTEMPCOTRIM_Msk 0x001E0000
#define AM_REG_OTP_INFO1_POWERSTATE16_CORELDOACTTRIM_S 7
#define AM_REG_OTP_INFO1_POWERSTATE16_CORELDOACTTRIM_M 0x0001FF80
#define AM_REG_OTP_INFO1_POWERSTATE16_CORELDOACTTRIM(n) (((uint32_t)(n) << 7) & 0x0001FF80)
#define AM_REG_OTP_INFO1_POWERSTATE16_CORELDOACTTRIM_Pos 7
#define AM_REG_OTP_INFO1_POWERSTATE16_CORELDOACTTRIM_Msk 0x0001FF80
#define AM_REG_OTP_INFO1_POWERSTATE16_TVRGFACTTRIM_S 0
#define AM_REG_OTP_INFO1_POWERSTATE16_TVRGFACTTRIM_M 0x0000007F
#define AM_REG_OTP_INFO1_POWERSTATE16_TVRGFACTTRIM(n) (((uint32_t)(n) << 0) & 0x0000007F)
#define AM_REG_OTP_INFO1_POWERSTATE16_TVRGFACTTRIM_Pos 0
#define AM_REG_OTP_INFO1_POWERSTATE16_TVRGFACTTRIM_Msk 0x0000007F

// POWERSTATE17 - Power state register. CPU LP mode, GPU or SDIO on, 0C to 50C.
#define AM_REG_OTP_INFO1_POWERSTATE17_RESVD29_S 29
#define AM_REG_OTP_INFO1_POWERSTATE17_RESVD29_M 0xE0000000
#define AM_REG_OTP_INFO1_POWERSTATE17_RESVD29(n) (((uint32_t)(n) << 29) & 0xE0000000)
#define AM_REG_OTP_INFO1_POWERSTATE17_RESVD29_Pos 29
#define AM_REG_OTP_INFO1_POWERSTATE17_RESVD29_Msk 0xE0000000
#define AM_REG_OTP_INFO1_POWERSTATE17_TVRGCVREFSEL_S 28
#define AM_REG_OTP_INFO1_POWERSTATE17_TVRGCVREFSEL_M 0x10000000
#define AM_REG_OTP_INFO1_POWERSTATE17_TVRGCVREFSEL(n) (((uint32_t)(n) << 28) & 0x10000000)
#define AM_REG_OTP_INFO1_POWERSTATE17_TVRGCVREFSEL_Pos 28
#define AM_REG_OTP_INFO1_POWERSTATE17_TVRGCVREFSEL_Msk 0x10000000
#define AM_REG_OTP_INFO1_POWERSTATE17_TVRGCACTTRIM_S 21
#define AM_REG_OTP_INFO1_POWERSTATE17_TVRGCACTTRIM_M 0x0FE00000
#define AM_REG_OTP_INFO1_POWERSTATE17_TVRGCACTTRIM(n) (((uint32_t)(n) << 21) & 0x0FE00000)
#define AM_REG_OTP_INFO1_POWERSTATE17_TVRGCACTTRIM_Pos 21
#define AM_REG_OTP_INFO1_POWERSTATE17_TVRGCACTTRIM_Msk 0x0FE00000
#define AM_REG_OTP_INFO1_POWERSTATE17_CORELDOTEMPCOTRIM_S 17
#define AM_REG_OTP_INFO1_POWERSTATE17_CORELDOTEMPCOTRIM_M 0x001E0000
#define AM_REG_OTP_INFO1_POWERSTATE17_CORELDOTEMPCOTRIM(n) (((uint32_t)(n) << 17) & 0x001E0000)
#define AM_REG_OTP_INFO1_POWERSTATE17_CORELDOTEMPCOTRIM_Pos 17
#define AM_REG_OTP_INFO1_POWERSTATE17_CORELDOTEMPCOTRIM_Msk 0x001E0000
#define AM_REG_OTP_INFO1_POWERSTATE17_CORELDOACTTRIM_S 7
#define AM_REG_OTP_INFO1_POWERSTATE17_CORELDOACTTRIM_M 0x0001FF80
#define AM_REG_OTP_INFO1_POWERSTATE17_CORELDOACTTRIM(n) (((uint32_t)(n) << 7) & 0x0001FF80)
#define AM_REG_OTP_INFO1_POWERSTATE17_CORELDOACTTRIM_Pos 7
#define AM_REG_OTP_INFO1_POWERSTATE17_CORELDOACTTRIM_Msk 0x0001FF80
#define AM_REG_OTP_INFO1_POWERSTATE17_TVRGFACTTRIM_S 0
#define AM_REG_OTP_INFO1_POWERSTATE17_TVRGFACTTRIM_M 0x0000007F
#define AM_REG_OTP_INFO1_POWERSTATE17_TVRGFACTTRIM(n) (((uint32_t)(n) << 0) & 0x0000007F)
#define AM_REG_OTP_INFO1_POWERSTATE17_TVRGFACTTRIM_Pos 0
#define AM_REG_OTP_INFO1_POWERSTATE17_TVRGFACTTRIM_Msk 0x0000007F

// POWERSTATE18 - Power state register. CPU LP mode, GPU or SDIO on, -20C to 0C.
#define AM_REG_OTP_INFO1_POWERSTATE18_RESVD29_S 29
#define AM_REG_OTP_INFO1_POWERSTATE18_RESVD29_M 0xE0000000
#define AM_REG_OTP_INFO1_POWERSTATE18_RESVD29(n) (((uint32_t)(n) << 29) & 0xE0000000)
#define AM_REG_OTP_INFO1_POWERSTATE18_RESVD29_Pos 29
#define AM_REG_OTP_INFO1_POWERSTATE18_RESVD29_Msk 0xE0000000
#define AM_REG_OTP_INFO1_POWERSTATE18_TVRGCVREFSEL_S 28
#define AM_REG_OTP_INFO1_POWERSTATE18_TVRGCVREFSEL_M 0x10000000
#define AM_REG_OTP_INFO1_POWERSTATE18_TVRGCVREFSEL(n) (((uint32_t)(n) << 28) & 0x10000000)
#define AM_REG_OTP_INFO1_POWERSTATE18_TVRGCVREFSEL_Pos 28
#define AM_REG_OTP_INFO1_POWERSTATE18_TVRGCVREFSEL_Msk 0x10000000
#define AM_REG_OTP_INFO1_POWERSTATE18_TVRGCACTTRIM_S 21
#define AM_REG_OTP_INFO1_POWERSTATE18_TVRGCACTTRIM_M 0x0FE00000
#define AM_REG_OTP_INFO1_POWERSTATE18_TVRGCACTTRIM(n) (((uint32_t)(n) << 21) & 0x0FE00000)
#define AM_REG_OTP_INFO1_POWERSTATE18_TVRGCACTTRIM_Pos 21
#define AM_REG_OTP_INFO1_POWERSTATE18_TVRGCACTTRIM_Msk 0x0FE00000
#define AM_REG_OTP_INFO1_POWERSTATE18_CORELDOTEMPCOTRIM_S 17
#define AM_REG_OTP_INFO1_POWERSTATE18_CORELDOTEMPCOTRIM_M 0x001E0000
#define AM_REG_OTP_INFO1_POWERSTATE18_CORELDOTEMPCOTRIM(n) (((uint32_t)(n) << 17) & 0x001E0000)
#define AM_REG_OTP_INFO1_POWERSTATE18_CORELDOTEMPCOTRIM_Pos 17
#define AM_REG_OTP_INFO1_POWERSTATE18_CORELDOTEMPCOTRIM_Msk 0x001E0000
#define AM_REG_OTP_INFO1_POWERSTATE18_CORELDOACTTRIM_S 7
#define AM_REG_OTP_INFO1_POWERSTATE18_CORELDOACTTRIM_M 0x0001FF80
#define AM_REG_OTP_INFO1_POWERSTATE18_CORELDOACTTRIM(n) (((uint32_t)(n) << 7) & 0x0001FF80)
#define AM_REG_OTP_INFO1_POWERSTATE18_CORELDOACTTRIM_Pos 7
#define AM_REG_OTP_INFO1_POWERSTATE18_CORELDOACTTRIM_Msk 0x0001FF80
#define AM_REG_OTP_INFO1_POWERSTATE18_TVRGFACTTRIM_S 0
#define AM_REG_OTP_INFO1_POWERSTATE18_TVRGFACTTRIM_M 0x0000007F
#define AM_REG_OTP_INFO1_POWERSTATE18_TVRGFACTTRIM(n) (((uint32_t)(n) << 0) & 0x0000007F)
#define AM_REG_OTP_INFO1_POWERSTATE18_TVRGFACTTRIM_Pos 0
#define AM_REG_OTP_INFO1_POWERSTATE18_TVRGFACTTRIM_Msk 0x0000007F

// POWERSTATE19 - Power state register. CPU LP mode, GPU or SDIO on, -40C to -20C.
#define AM_REG_OTP_INFO1_POWERSTATE19_RESVD29_S 29
#define AM_REG_OTP_INFO1_POWERSTATE19_RESVD29_M 0xE0000000
#define AM_REG_OTP_INFO1_POWERSTATE19_RESVD29(n) (((uint32_t)(n) << 29) & 0xE0000000)
#define AM_REG_OTP_INFO1_POWERSTATE19_RESVD29_Pos 29
#define AM_REG_OTP_INFO1_POWERSTATE19_RESVD29_Msk 0xE0000000
#define AM_REG_OTP_INFO1_POWERSTATE19_TVRGCVREFSEL_S 28
#define AM_REG_OTP_INFO1_POWERSTATE19_TVRGCVREFSEL_M 0x10000000
#define AM_REG_OTP_INFO1_POWERSTATE19_TVRGCVREFSEL(n) (((uint32_t)(n) << 28) & 0x10000000)
#define AM_REG_OTP_INFO1_POWERSTATE19_TVRGCVREFSEL_Pos 28
#define AM_REG_OTP_INFO1_POWERSTATE19_TVRGCVREFSEL_Msk 0x10000000
#define AM_REG_OTP_INFO1_POWERSTATE19_TVRGCACTTRIM_S 21
#define AM_REG_OTP_INFO1_POWERSTATE19_TVRGCACTTRIM_M 0x0FE00000
#define AM_REG_OTP_INFO1_POWERSTATE19_TVRGCACTTRIM(n) (((uint32_t)(n) << 21) & 0x0FE00000)
#define AM_REG_OTP_INFO1_POWERSTATE19_TVRGCACTTRIM_Pos 21
#define AM_REG_OTP_INFO1_POWERSTATE19_TVRGCACTTRIM_Msk 0x0FE00000
#define AM_REG_OTP_INFO1_POWERSTATE19_CORELDOTEMPCOTRIM_S 17
#define AM_REG_OTP_INFO1_POWERSTATE19_CORELDOTEMPCOTRIM_M 0x001E0000
#define AM_REG_OTP_INFO1_POWERSTATE19_CORELDOTEMPCOTRIM(n) (((uint32_t)(n) << 17) & 0x001E0000)
#define AM_REG_OTP_INFO1_POWERSTATE19_CORELDOTEMPCOTRIM_Pos 17
#define AM_REG_OTP_INFO1_POWERSTATE19_CORELDOTEMPCOTRIM_Msk 0x001E0000
#define AM_REG_OTP_INFO1_POWERSTATE19_CORELDOACTTRIM_S 7
#define AM_REG_OTP_INFO1_POWERSTATE19_CORELDOACTTRIM_M 0x0001FF80
#define AM_REG_OTP_INFO1_POWERSTATE19_CORELDOACTTRIM(n) (((uint32_t)(n) << 7) & 0x0001FF80)
#define AM_REG_OTP_INFO1_POWERSTATE19_CORELDOACTTRIM_Pos 7
#define AM_REG_OTP_INFO1_POWERSTATE19_CORELDOACTTRIM_Msk 0x0001FF80
#define AM_REG_OTP_INFO1_POWERSTATE19_TVRGFACTTRIM_S 0
#define AM_REG_OTP_INFO1_POWERSTATE19_TVRGFACTTRIM_M 0x0000007F
#define AM_REG_OTP_INFO1_POWERSTATE19_TVRGFACTTRIM(n) (((uint32_t)(n) << 0) & 0x0000007F)
#define AM_REG_OTP_INFO1_POWERSTATE19_TVRGFACTTRIM_Pos 0
#define AM_REG_OTP_INFO1_POWERSTATE19_TVRGFACTTRIM_Msk 0x0000007F

// GPUVDDCTON - GPU VDDC Ton Adjustments
#define AM_REG_OTP_INFO1_GPUVDDCTON_RESVD_S 25
#define AM_REG_OTP_INFO1_GPUVDDCTON_RESVD_M 0xFE000000
#define AM_REG_OTP_INFO1_GPUVDDCTON_RESVD(n) (((uint32_t)(n) << 25) & 0xFE000000)
#define AM_REG_OTP_INFO1_GPUVDDCTON_RESVD_Pos 25
#define AM_REG_OTP_INFO1_GPUVDDCTON_RESVD_Msk 0xFE000000
#define AM_REG_OTP_INFO1_GPUVDDCTON_PWRSTATE12VDDCTON_S 20
#define AM_REG_OTP_INFO1_GPUVDDCTON_PWRSTATE12VDDCTON_M 0x01F00000
#define AM_REG_OTP_INFO1_GPUVDDCTON_PWRSTATE12VDDCTON(n) (((uint32_t)(n) << 20) & 0x01F00000)
#define AM_REG_OTP_INFO1_GPUVDDCTON_PWRSTATE12VDDCTON_Pos 20
#define AM_REG_OTP_INFO1_GPUVDDCTON_PWRSTATE12VDDCTON_Msk 0x01F00000
#define AM_REG_OTP_INFO1_GPUVDDCTON_GPUHPCPUHPVDDCTON_S 15
#define AM_REG_OTP_INFO1_GPUVDDCTON_GPUHPCPUHPVDDCTON_M 0x000F8000
#define AM_REG_OTP_INFO1_GPUVDDCTON_GPUHPCPUHPVDDCTON(n) (((uint32_t)(n) << 15) & 0x000F8000)
#define AM_REG_OTP_INFO1_GPUVDDCTON_GPUHPCPUHPVDDCTON_Pos 15
#define AM_REG_OTP_INFO1_GPUVDDCTON_GPUHPCPUHPVDDCTON_Msk 0x000F8000
#define AM_REG_OTP_INFO1_GPUVDDCTON_GPUHPCPULPVDDCTON_S 10
#define AM_REG_OTP_INFO1_GPUVDDCTON_GPUHPCPULPVDDCTON_M 0x00007C00
#define AM_REG_OTP_INFO1_GPUVDDCTON_GPUHPCPULPVDDCTON(n) (((uint32_t)(n) << 10) & 0x00007C00)
#define AM_REG_OTP_INFO1_GPUVDDCTON_GPUHPCPULPVDDCTON_Pos 10
#define AM_REG_OTP_INFO1_GPUVDDCTON_GPUHPCPULPVDDCTON_Msk 0x00007C00
#define AM_REG_OTP_INFO1_GPUVDDCTON_GPULPCPUHPVDDCTON_S 5
#define AM_REG_OTP_INFO1_GPUVDDCTON_GPULPCPUHPVDDCTON_M 0x000003E0
#define AM_REG_OTP_INFO1_GPUVDDCTON_GPULPCPUHPVDDCTON(n) (((uint32_t)(n) << 5) & 0x000003E0)
#define AM_REG_OTP_INFO1_GPUVDDCTON_GPULPCPUHPVDDCTON_Pos 5
#define AM_REG_OTP_INFO1_GPUVDDCTON_GPULPCPUHPVDDCTON_Msk 0x000003E0
#define AM_REG_OTP_INFO1_GPUVDDCTON_GPULPCPULPVDDCTON_S 0
#define AM_REG_OTP_INFO1_GPUVDDCTON_GPULPCPULPVDDCTON_M 0x0000001F
#define AM_REG_OTP_INFO1_GPUVDDCTON_GPULPCPULPVDDCTON(n) (((uint32_t)(n) << 0) & 0x0000001F)
#define AM_REG_OTP_INFO1_GPUVDDCTON_GPULPCPULPVDDCTON_Pos 0
#define AM_REG_OTP_INFO1_GPUVDDCTON_GPULPCPULPVDDCTON_Msk 0x0000001F

// GPUVDDFTON - GPU VDDF Ton adjustments
#define AM_REG_OTP_INFO1_GPUVDDFTON_RESVD_S 20
#define AM_REG_OTP_INFO1_GPUVDDFTON_RESVD_M 0xFFF00000
#define AM_REG_OTP_INFO1_GPUVDDFTON_RESVD(n) (((uint32_t)(n) << 20) & 0xFFF00000)
#define AM_REG_OTP_INFO1_GPUVDDFTON_RESVD_Pos 20
#define AM_REG_OTP_INFO1_GPUVDDFTON_RESVD_Msk 0xFFF00000
#define AM_REG_OTP_INFO1_GPUVDDFTON_GPUHPCPUHPVDDFTON_S 15
#define AM_REG_OTP_INFO1_GPUVDDFTON_GPUHPCPUHPVDDFTON_M 0x000F8000
#define AM_REG_OTP_INFO1_GPUVDDFTON_GPUHPCPUHPVDDFTON(n) (((uint32_t)(n) << 15) & 0x000F8000)
#define AM_REG_OTP_INFO1_GPUVDDFTON_GPUHPCPUHPVDDFTON_Pos 15
#define AM_REG_OTP_INFO1_GPUVDDFTON_GPUHPCPUHPVDDFTON_Msk 0x000F8000
#define AM_REG_OTP_INFO1_GPUVDDFTON_GPUHPCPULPVDDFTON_S 10
#define AM_REG_OTP_INFO1_GPUVDDFTON_GPUHPCPULPVDDFTON_M 0x00007C00
#define AM_REG_OTP_INFO1_GPUVDDFTON_GPUHPCPULPVDDFTON(n) (((uint32_t)(n) << 10) & 0x00007C00)
#define AM_REG_OTP_INFO1_GPUVDDFTON_GPUHPCPULPVDDFTON_Pos 10
#define AM_REG_OTP_INFO1_GPUVDDFTON_GPUHPCPULPVDDFTON_Msk 0x00007C00
#define AM_REG_OTP_INFO1_GPUVDDFTON_GPULPCPUHPVDDFTON_S 5
#define AM_REG_OTP_INFO1_GPUVDDFTON_GPULPCPUHPVDDFTON_M 0x000003E0
#define AM_REG_OTP_INFO1_GPUVDDFTON_GPULPCPUHPVDDFTON(n) (((uint32_t)(n) << 5) & 0x000003E0)
#define AM_REG_OTP_INFO1_GPUVDDFTON_GPULPCPUHPVDDFTON_Pos 5
#define AM_REG_OTP_INFO1_GPUVDDFTON_GPULPCPUHPVDDFTON_Msk 0x000003E0
#define AM_REG_OTP_INFO1_GPUVDDFTON_GPULPCPULPVDDFTON_S 0
#define AM_REG_OTP_INFO1_GPUVDDFTON_GPULPCPULPVDDFTON_M 0x0000001F
#define AM_REG_OTP_INFO1_GPUVDDFTON_GPULPCPULPVDDFTON(n) (((uint32_t)(n) << 0) & 0x0000001F)
#define AM_REG_OTP_INFO1_GPUVDDFTON_GPULPCPULPVDDFTON_Pos 0
#define AM_REG_OTP_INFO1_GPUVDDFTON_GPULPCPULPVDDFTON_Msk 0x0000001F

// STMTON - STM Ton adjustments register
#define AM_REG_OTP_INFO1_STMTON_RESVD_S 25
#define AM_REG_OTP_INFO1_STMTON_RESVD_M 0xFE000000
#define AM_REG_OTP_INFO1_STMTON_RESVD(n) (((uint32_t)(n) << 25) & 0xFE000000)
#define AM_REG_OTP_INFO1_STMTON_RESVD_Pos 25
#define AM_REG_OTP_INFO1_STMTON_RESVD_Msk 0xFE000000
#define AM_REG_OTP_INFO1_STMTON_PWRSTATE8VDDCTON_S 20
#define AM_REG_OTP_INFO1_STMTON_PWRSTATE8VDDCTON_M 0x01F00000
#define AM_REG_OTP_INFO1_STMTON_PWRSTATE8VDDCTON(n) (((uint32_t)(n) << 20) & 0x01F00000)
#define AM_REG_OTP_INFO1_STMTON_PWRSTATE8VDDCTON_Pos 20
#define AM_REG_OTP_INFO1_STMTON_PWRSTATE8VDDCTON_Msk 0x01F00000
#define AM_REG_OTP_INFO1_STMTON_STMCPUHPVDDFTON_S 15
#define AM_REG_OTP_INFO1_STMTON_STMCPUHPVDDFTON_M 0x000F8000
#define AM_REG_OTP_INFO1_STMTON_STMCPUHPVDDFTON(n) (((uint32_t)(n) << 15) & 0x000F8000)
#define AM_REG_OTP_INFO1_STMTON_STMCPUHPVDDFTON_Pos 15
#define AM_REG_OTP_INFO1_STMTON_STMCPUHPVDDFTON_Msk 0x000F8000
#define AM_REG_OTP_INFO1_STMTON_STMCPULPVDDFTON_S 10
#define AM_REG_OTP_INFO1_STMTON_STMCPULPVDDFTON_M 0x00007C00
#define AM_REG_OTP_INFO1_STMTON_STMCPULPVDDFTON(n) (((uint32_t)(n) << 10) & 0x00007C00)
#define AM_REG_OTP_INFO1_STMTON_STMCPULPVDDFTON_Pos 10
#define AM_REG_OTP_INFO1_STMTON_STMCPULPVDDFTON_Msk 0x00007C00
#define AM_REG_OTP_INFO1_STMTON_STMCPUHPVDDCTON_S 5
#define AM_REG_OTP_INFO1_STMTON_STMCPUHPVDDCTON_M 0x000003E0
#define AM_REG_OTP_INFO1_STMTON_STMCPUHPVDDCTON(n) (((uint32_t)(n) << 5) & 0x000003E0)
#define AM_REG_OTP_INFO1_STMTON_STMCPUHPVDDCTON_Pos 5
#define AM_REG_OTP_INFO1_STMTON_STMCPUHPVDDCTON_Msk 0x000003E0
#define AM_REG_OTP_INFO1_STMTON_STMCPULPVDDCTON_S 0
#define AM_REG_OTP_INFO1_STMTON_STMCPULPVDDCTON_M 0x0000001F
#define AM_REG_OTP_INFO1_STMTON_STMCPULPVDDCTON(n) (((uint32_t)(n) << 0) & 0x0000001F)
#define AM_REG_OTP_INFO1_STMTON_STMCPULPVDDCTON_Pos 0
#define AM_REG_OTP_INFO1_STMTON_STMCPULPVDDCTON_Msk 0x0000001F

// DEFAULTTON - Memory LDO configuration fields
#define AM_REG_OTP_INFO1_DEFAULTTON_RESVD_S 20
#define AM_REG_OTP_INFO1_DEFAULTTON_RESVD_M 0xFFF00000
#define AM_REG_OTP_INFO1_DEFAULTTON_RESVD(n) (((uint32_t)(n) << 20) & 0xFFF00000)
#define AM_REG_OTP_INFO1_DEFAULTTON_RESVD_Pos 20
#define AM_REG_OTP_INFO1_DEFAULTTON_RESVD_Msk 0xFFF00000
#define AM_REG_OTP_INFO1_DEFAULTTON_VDDFACTHIGHTON_S 15
#define AM_REG_OTP_INFO1_DEFAULTTON_VDDFACTHIGHTON_M 0x000F8000
#define AM_REG_OTP_INFO1_DEFAULTTON_VDDFACTHIGHTON(n) (((uint32_t)(n) << 15) & 0x000F8000)
#define AM_REG_OTP_INFO1_DEFAULTTON_VDDFACTHIGHTON_Pos 15
#define AM_REG_OTP_INFO1_DEFAULTTON_VDDFACTHIGHTON_Msk 0x000F8000
#define AM_REG_OTP_INFO1_DEFAULTTON_VDDFACTLOWTON_S 10
#define AM_REG_OTP_INFO1_DEFAULTTON_VDDFACTLOWTON_M 0x00007C00
#define AM_REG_OTP_INFO1_DEFAULTTON_VDDFACTLOWTON(n) (((uint32_t)(n) << 10) & 0x00007C00)
#define AM_REG_OTP_INFO1_DEFAULTTON_VDDFACTLOWTON_Pos 10
#define AM_REG_OTP_INFO1_DEFAULTTON_VDDFACTLOWTON_Msk 0x00007C00
#define AM_REG_OTP_INFO1_DEFAULTTON_VDDCACTHIGHTON_S 5
#define AM_REG_OTP_INFO1_DEFAULTTON_VDDCACTHIGHTON_M 0x000003E0
#define AM_REG_OTP_INFO1_DEFAULTTON_VDDCACTHIGHTON(n) (((uint32_t)(n) << 5) & 0x000003E0)
#define AM_REG_OTP_INFO1_DEFAULTTON_VDDCACTHIGHTON_Pos 5
#define AM_REG_OTP_INFO1_DEFAULTTON_VDDCACTHIGHTON_Msk 0x000003E0
#define AM_REG_OTP_INFO1_DEFAULTTON_VDDCACTLOWTON_S 0
#define AM_REG_OTP_INFO1_DEFAULTTON_VDDCACTLOWTON_M 0x0000001F
#define AM_REG_OTP_INFO1_DEFAULTTON_VDDCACTLOWTON(n) (((uint32_t)(n) << 0) & 0x0000001F)
#define AM_REG_OTP_INFO1_DEFAULTTON_VDDCACTLOWTON_Pos 0
#define AM_REG_OTP_INFO1_DEFAULTTON_VDDCACTLOWTON_Msk 0x0000001F

// VDDCLVACTTRIMADJ - VDDCLV Active Trim Voltage Trim Adjust
#define AM_REG_OTP_INFO1_VDDCLVACTTRIMADJ_RESVD_S 28
#define AM_REG_OTP_INFO1_VDDCLVACTTRIMADJ_RESVD_M 0xF0000000
#define AM_REG_OTP_INFO1_VDDCLVACTTRIMADJ_RESVD(n) (((uint32_t)(n) << 28) & 0xF0000000)
#define AM_REG_OTP_INFO1_VDDCLVACTTRIMADJ_RESVD_Pos 28
#define AM_REG_OTP_INFO1_VDDCLVACTTRIMADJ_RESVD_Msk 0xF0000000
#define AM_REG_OTP_INFO1_VDDCLVACTTRIMADJ_TRIM3_S 21
#define AM_REG_OTP_INFO1_VDDCLVACTTRIMADJ_TRIM3_M 0x0FE00000
#define AM_REG_OTP_INFO1_VDDCLVACTTRIMADJ_TRIM3(n) (((uint32_t)(n) << 21) & 0x0FE00000)
#define AM_REG_OTP_INFO1_VDDCLVACTTRIMADJ_TRIM3_Pos 21
#define AM_REG_OTP_INFO1_VDDCLVACTTRIMADJ_TRIM3_Msk 0x0FE00000
#define AM_REG_OTP_INFO1_VDDCLVACTTRIMADJ_TRIM2_S 14
#define AM_REG_OTP_INFO1_VDDCLVACTTRIMADJ_TRIM2_M 0x001FC000
#define AM_REG_OTP_INFO1_VDDCLVACTTRIMADJ_TRIM2(n) (((uint32_t)(n) << 14) & 0x001FC000)
#define AM_REG_OTP_INFO1_VDDCLVACTTRIMADJ_TRIM2_Pos 14
#define AM_REG_OTP_INFO1_VDDCLVACTTRIMADJ_TRIM2_Msk 0x001FC000
#define AM_REG_OTP_INFO1_VDDCLVACTTRIMADJ_TRIM1_S 7
#define AM_REG_OTP_INFO1_VDDCLVACTTRIMADJ_TRIM1_M 0x00003F80
#define AM_REG_OTP_INFO1_VDDCLVACTTRIMADJ_TRIM1(n) (((uint32_t)(n) << 7) & 0x00003F80)
#define AM_REG_OTP_INFO1_VDDCLVACTTRIMADJ_TRIM1_Pos 7
#define AM_REG_OTP_INFO1_VDDCLVACTTRIMADJ_TRIM1_Msk 0x00003F80
#define AM_REG_OTP_INFO1_VDDCLVACTTRIMADJ_TRIM0_S 0
#define AM_REG_OTP_INFO1_VDDCLVACTTRIMADJ_TRIM0_M 0x0000007F
#define AM_REG_OTP_INFO1_VDDCLVACTTRIMADJ_TRIM0(n) (((uint32_t)(n) << 0) & 0x0000007F)
#define AM_REG_OTP_INFO1_VDDCLVACTTRIMADJ_TRIM0_Pos 0
#define AM_REG_OTP_INFO1_VDDCLVACTTRIMADJ_TRIM0_Msk 0x0000007F

// POWERSTATE_RSVD_D1 - Power state reserved register
#define AM_REG_OTP_INFO1_POWERSTATE_RSVD_D1_RESVD_S 0
#define AM_REG_OTP_INFO1_POWERSTATE_RSVD_D1_RESVD_M 0xFFFFFFFF
#define AM_REG_OTP_INFO1_POWERSTATE_RSVD_D1_RESVD(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
#define AM_REG_OTP_INFO1_POWERSTATE_RSVD_D1_RESVD_Pos 0
#define AM_REG_OTP_INFO1_POWERSTATE_RSVD_D1_RESVD_Msk 0xFFFFFFFF

// POWERSTATE_RSVD_D2 - Power state reserved register
#define AM_REG_OTP_INFO1_POWERSTATE_RSVD_D2_RESVD_S 0
#define AM_REG_OTP_INFO1_POWERSTATE_RSVD_D2_RESVD_M 0xFFFFFFFF
#define AM_REG_OTP_INFO1_POWERSTATE_RSVD_D2_RESVD(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
#define AM_REG_OTP_INFO1_POWERSTATE_RSVD_D2_RESVD_Pos 0
#define AM_REG_OTP_INFO1_POWERSTATE_RSVD_D2_RESVD_Msk 0xFFFFFFFF

// POWERSTATE_RSVD_D3 - Power state reserved register
#define AM_REG_OTP_INFO1_POWERSTATE_RSVD_D3_RESVD_S 0
#define AM_REG_OTP_INFO1_POWERSTATE_RSVD_D3_RESVD_M 0xFFFFFFFF
#define AM_REG_OTP_INFO1_POWERSTATE_RSVD_D3_RESVD(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
#define AM_REG_OTP_INFO1_POWERSTATE_RSVD_D3_RESVD_Pos 0
#define AM_REG_OTP_INFO1_POWERSTATE_RSVD_D3_RESVD_Msk 0xFFFFFFFF

// MEMLDOCONFIG - Memory LDO configuration fields
#define AM_REG_OTP_INFO1_MEMLDOCONFIG_RESVD_S 20
#define AM_REG_OTP_INFO1_MEMLDOCONFIG_RESVD_M 0xFFF00000
#define AM_REG_OTP_INFO1_MEMLDOCONFIG_RESVD(n) (((uint32_t)(n) << 20) & 0xFFF00000)
#define AM_REG_OTP_INFO1_MEMLDOCONFIG_RESVD_Pos 20
#define AM_REG_OTP_INFO1_MEMLDOCONFIG_RESVD_Msk 0xFFF00000
#define AM_REG_OTP_INFO1_MEMLDOCONFIG_DFLTMEMLDOACTTRIM_S 14
#define AM_REG_OTP_INFO1_MEMLDOCONFIG_DFLTMEMLDOACTTRIM_M 0x000FC000
#define AM_REG_OTP_INFO1_MEMLDOCONFIG_DFLTMEMLDOACTTRIM(n) (((uint32_t)(n) << 14) & 0x000FC000)
#define AM_REG_OTP_INFO1_MEMLDOCONFIG_DFLTMEMLDOACTTRIM_Pos 14
#define AM_REG_OTP_INFO1_MEMLDOCONFIG_DFLTMEMLDOACTTRIM_Msk 0x000FC000
#define AM_REG_OTP_INFO1_MEMLDOCONFIG_TVGRFPWLOFFSET_S 8
#define AM_REG_OTP_INFO1_MEMLDOCONFIG_TVGRFPWLOFFSET_M 0x00003F00
#define AM_REG_OTP_INFO1_MEMLDOCONFIG_TVGRFPWLOFFSET(n) (((uint32_t)(n) << 8) & 0x00003F00)
#define AM_REG_OTP_INFO1_MEMLDOCONFIG_TVGRFPWLOFFSET_Pos 8
#define AM_REG_OTP_INFO1_MEMLDOCONFIG_TVGRFPWLOFFSET_Msk 0x00003F00
#define AM_REG_OTP_INFO1_MEMLDOCONFIG_MEMLDOACTTRIM_S 2
#define AM_REG_OTP_INFO1_MEMLDOCONFIG_MEMLDOACTTRIM_M 0x000000FC
#define AM_REG_OTP_INFO1_MEMLDOCONFIG_MEMLDOACTTRIM(n) (((uint32_t)(n) << 2) & 0x000000FC)
#define AM_REG_OTP_INFO1_MEMLDOCONFIG_MEMLDOACTTRIM_Pos 2
#define AM_REG_OTP_INFO1_MEMLDOCONFIG_MEMLDOACTTRIM_Msk 0x000000FC
#define AM_REG_OTP_INFO1_MEMLDOCONFIG_MEMLDOD2ASPARE_S 0
#define AM_REG_OTP_INFO1_MEMLDOCONFIG_MEMLDOD2ASPARE_M 0x00000003
#define AM_REG_OTP_INFO1_MEMLDOCONFIG_MEMLDOD2ASPARE(n) (((uint32_t)(n) << 0) & 0x00000003)
#define AM_REG_OTP_INFO1_MEMLDOCONFIG_MEMLDOD2ASPARE_Pos 0
#define AM_REG_OTP_INFO1_MEMLDOCONFIG_MEMLDOD2ASPARE_Msk 0x00000003

#endif
